gpu: nvgpu: modify gr.falcon.dump_stats

- Add gm20b_gr_falcon_gpccs_dump_stats() to print gpccs context switch
mailbox register values for all gpcs.
- Make gm20b_gr_falcon_fecs_dump_stats() a static function
- Add gm20b_gr_falcon_dump_stats() to trigger
gm20b_gr_falcon_fecs_dump_stats() and gm20b_gr_falcon_gpccs_dump_stats()
- Update legacy chips gr.falcon.dump_stats() to
gm20b_gr_falcon_dump_stats().

JIRA NVGPU-5597

Change-Id: I992c6432f3c2e3049bacc953f9b53ff6c4aa2f36
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2357470
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Seema Khowala <seemaj@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.h

@@ -38,7 +38,7 @@ u32 gm20b_gr_falcon_fecs_host_intr_status(struct gk20a *g,
 			struct nvgpu_fecs_host_intr_status *fecs_host_intr);
 u32 gm20b_gr_falcon_fecs_base_addr(void);
 u32 gm20b_gr_falcon_gpccs_base_addr(void);
-void gm20b_gr_falcon_fecs_dump_stats(struct gk20a *g);
+void gm20b_gr_falcon_dump_stats(struct gk20a *g);
 u32 gm20b_gr_falcon_get_fecs_ctx_state_store_major_rev_id(struct gk20a *g);
 u32 gm20b_gr_falcon_get_fecs_ctxsw_mailbox_size(void);
 void gm20b_gr_falcon_start_gpccs(struct gk20a *g);

drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b_fusa.c

@@ -28,11 +28,11 @@
 #include <nvgpu/soc.h>
 #include <nvgpu/static_analysis.h>
 #include <nvgpu/gr/gr_utils.h>
+#include <nvgpu/gr/config.h>
 #include <nvgpu/pmu/clk/clk.h>
 
 #include "gr_falcon_gm20b.h"
 #include "common/gr/gr_falcon_priv.h"
-#include <nvgpu/gr/gr_utils.h>
 
 #include <nvgpu/hw/gm20b/hw_gr_gm20b.h>
 
@@ -596,7 +596,7 @@ u32 gm20b_gr_falcon_gpccs_base_addr(void)
 	return gr_gpcs_gpccs_irqsset_r();
 }
 
-void gm20b_gr_falcon_fecs_dump_stats(struct gk20a *g)
+static void gm20b_gr_falcon_fecs_dump_stats(struct gk20a *g)
 {
 	unsigned int i;
 
@@ -605,11 +605,38 @@ void gm20b_gr_falcon_fecs_dump_stats(struct gk20a *g)
 #endif
 
 	for (i = 0; i < g->ops.gr.falcon.fecs_ctxsw_mailbox_size(); i++) {
-		nvgpu_err(g, "gr_fecs_ctxsw_mailbox_r(%d) : 0x%x",
+		nvgpu_err(g, "gr_fecs_ctxsw_mailbox_r(%d): 0x%x",
 			i, nvgpu_readl(g, gr_fecs_ctxsw_mailbox_r(i)));
 	}
 }
 
+static void gm20b_gr_falcon_gpccs_dump_stats(struct gk20a *g)
+{
+	unsigned int i;
+	struct nvgpu_gr_config *gr_config = nvgpu_gr_get_config_ptr(g);
+	u32 gpc_count = nvgpu_gr_config_get_gpc_count(gr_config);
+	u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
+	u32 gpc = 0U, offset = 0U;
+
+	for (gpc = 0U; gpc < gpc_count; gpc++) {
+		offset = nvgpu_safe_mult_u32(gpc_stride, gpc);
+		for (i = 0U; i < gr_gpccs_ctxsw_mailbox__size_1_v(); i++) {
+			nvgpu_err(g,
+				"gr_gpc%d_gpccs_ctxsw_mailbox_r(%d): 0x%x",
+				gpc, i,
+				nvgpu_readl(g, nvgpu_safe_add_u32(
+					gr_gpc0_gpccs_ctxsw_mailbox_r(i),
+					offset)));
+		}
+	}
+}
+
+void gm20b_gr_falcon_dump_stats(struct gk20a *g)
+{
+	gm20b_gr_falcon_fecs_dump_stats(g);
+	gm20b_gr_falcon_gpccs_dump_stats(g);
+}
+
 u32 gm20b_gr_falcon_get_fecs_ctx_state_store_major_rev_id(struct gk20a *g)
 {
 	return nvgpu_readl(g, gr_fecs_ctx_state_store_major_rev_id_r());

drivers/gpu/nvgpu/hal/init/hal_gm20b.c

@@ -515,7 +515,7 @@ static const struct gpu_ops gm20b_ops = {
 			.gpccs_base_addr = gm20b_gr_falcon_gpccs_base_addr,
 			.set_current_ctx_invalid =
 				gm20b_gr_falcon_set_current_ctx_invalid,
-			.dump_stats = gm20b_gr_falcon_fecs_dump_stats,
+			.dump_stats = gm20b_gr_falcon_dump_stats,
 			.fecs_ctxsw_mailbox_size =
 				gm20b_gr_falcon_get_fecs_ctxsw_mailbox_size,
 			.fecs_ctxsw_clear_mailbox =

drivers/gpu/nvgpu/hal/init/hal_gp10b.c

@@ -603,7 +603,7 @@ static const struct gpu_ops gp10b_ops = {
 			.gpccs_base_addr = gm20b_gr_falcon_gpccs_base_addr,
 			.set_current_ctx_invalid =
 				gm20b_gr_falcon_set_current_ctx_invalid,
-			.dump_stats = gm20b_gr_falcon_fecs_dump_stats,
+			.dump_stats = gm20b_gr_falcon_dump_stats,
 			.fecs_ctxsw_mailbox_size =
 				gm20b_gr_falcon_get_fecs_ctxsw_mailbox_size,
 			.fecs_ctxsw_clear_mailbox =

drivers/gpu/nvgpu/hal/init/hal_gv11b.c

@@ -766,7 +766,7 @@ NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 8_7))
 			.gpccs_base_addr = gm20b_gr_falcon_gpccs_base_addr,
 			.set_current_ctx_invalid =
 				gm20b_gr_falcon_set_current_ctx_invalid,
-			.dump_stats = gm20b_gr_falcon_fecs_dump_stats,
+			.dump_stats = gm20b_gr_falcon_dump_stats,
 			.fecs_ctxsw_mailbox_size =
 				gm20b_gr_falcon_get_fecs_ctxsw_mailbox_size,
 			.fecs_ctxsw_clear_mailbox =

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -789,7 +789,7 @@ static const struct gpu_ops tu104_ops = {
 			.gpccs_base_addr = gm20b_gr_falcon_gpccs_base_addr,
 			.set_current_ctx_invalid =
 				gm20b_gr_falcon_set_current_ctx_invalid,
-			.dump_stats = gm20b_gr_falcon_fecs_dump_stats,
+			.dump_stats = gm20b_gr_falcon_dump_stats,
 			.fecs_ctxsw_mailbox_size =
 				gm20b_gr_falcon_get_fecs_ctxsw_mailbox_size,
 			.fecs_ctxsw_clear_mailbox =

drivers/gpu/nvgpu/include/nvgpu/gops_gr.h

@@ -274,8 +274,10 @@ struct gops_gr_falcon {
 	 *
 	 * @param g [in]		Pointer to GPU driver struct.
 	 *
-	 * This function reads and prints all context switch mailbox
+	 * This function reads and prints all
-	 * register values. This is helpful for ucode debugging.
+	 * - fecs context switch mailbox values
+	 * - gpccs context switch mailbox values for all available gpcs
+	 * This is helpful for ucode debugging.
 	 */
 	void (*dump_stats)(struct gk20a *g);
 

drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -710,7 +710,10 @@
 		(nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32((i), 8U)))
 #define gr_gpccs_ctxsw_mailbox_r(i)\
 		(nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_gpccs_ctxsw_mailbox__size_1_v()                         (0x00000010U)
 #define gr_gpccs_ctxsw_mailbox_value_f(v)         ((U32(v) & 0xffffffffU) << 0U)
+#define gr_gpc0_gpccs_ctxsw_mailbox_r(i)\
+		(nvgpu_safe_add_u32(0x00502800U, nvgpu_safe_mult_u32((i), 4U)))
 #define gr_gpcs_swdx_bundle_cb_base_r()                            (0x00418e24U)
 #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_s()                          (32U)
 #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(v)\

drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -802,7 +802,10 @@
 		(nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32((i), 8U)))
 #define gr_gpccs_ctxsw_mailbox_r(i)\
 		(nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_gpccs_ctxsw_mailbox__size_1_v()                         (0x00000010U)
 #define gr_gpccs_ctxsw_mailbox_value_f(v)         ((U32(v) & 0xffffffffU) << 0U)
+#define gr_gpc0_gpccs_ctxsw_mailbox_r(i)\
+		(nvgpu_safe_add_u32(0x00502800U, nvgpu_safe_mult_u32((i), 4U)))
 #define gr_gpcs_swdx_bundle_cb_base_r()                            (0x00418e24U)
 #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_s()                          (32U)
 #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(v)\

drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h

@@ -1146,7 +1146,10 @@
 		(nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32((i), 8U)))
 #define gr_gpccs_ctxsw_mailbox_r(i)\
 		(nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_gpccs_ctxsw_mailbox__size_1_v()                         (0x00000010U)
 #define gr_gpccs_ctxsw_mailbox_value_f(v)         ((U32(v) & 0xffffffffU) << 0U)
+#define gr_gpc0_gpccs_ctxsw_mailbox_r(i)\
+		(nvgpu_safe_add_u32(0x00502800U, nvgpu_safe_mult_u32((i), 4U)))
 #define gr_gpcs_swdx_bundle_cb_base_r()                            (0x00418e24U)
 #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_s()                          (32U)
 #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(v)\

drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gr_tu104.h

@@ -878,7 +878,10 @@
 		(nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32((i), 8U)))
 #define gr_gpccs_ctxsw_mailbox_r(i)\
 		(nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32((i), 4U)))
+#define gr_gpccs_ctxsw_mailbox__size_1_v()                         (0x00000010U)
 #define gr_gpccs_ctxsw_mailbox_value_f(v)         ((U32(v) & 0xffffffffU) << 0U)
+#define gr_gpc0_gpccs_ctxsw_mailbox_r(i)\
+		(nvgpu_safe_add_u32(0x00502800U, nvgpu_safe_mult_u32((i), 4U)))
 #define gr_gpcs_swdx_bundle_cb_base_r()                            (0x00418e24U)
 #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_s()                          (32U)
 #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(v)\

userspace/units/fifo/nvgpu-fifo-common.c

@@ -120,6 +120,10 @@ static u32 stub_gv11b_gr_init_get_no_of_sm(struct gk20a *g)
 	return 8;
 }
 
+static void stub_gr_falcon_dump_stats(struct gk20a *g)
+{
+}
+
 #ifdef CONFIG_NVGPU_USERD
 static int stub_userd_setup_sw(struct gk20a *g)
 {
@@ -157,6 +161,7 @@ int test_fifo_init_support(struct unit_module *m, struct gk20a *g, void *args)
 
 	gv11b_init_hal(g);
 	g->ops.gr.init.get_no_of_sm = stub_gv11b_gr_init_get_no_of_sm;
+	g->ops.gr.falcon.dump_stats = stub_gr_falcon_dump_stats;
 
 	global_m = m;