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gpu: nvgpu: Enable ptimer

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This is enabling ptimer in mme_config and
mme_fe1_config by setting the corresponding
field.
Debugger is expected to make use of ptimer.
So this is required for nvgpu to enable ptimer
in the register.

Bug 3637441

Change-Id: Id596a87081753bcaf945e54444a8abbd025b3f76
Signed-off-by: Dinesh T <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2710632
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Dinesh T
2022-05-10 20:34:56 +00:00
committed by mobile promotions
parent ac4d8b9bff
commit fb466b5b25
6 changed files with 53 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/gpu/nvgpu/common/gr/obj_ctx.c
View File

@@ -907,6 +907,17 @@ int nvgpu_gr_obj_ctx_alloc(struct gk20a *g,
}
#endif
#ifdef CONFIG_NVGPU_NON_FUSA
if (g->ops.gr.init.enable_mme_config_ptimer != NULL) {
err = nvgpu_pg_elpg_protected_call(g,
g->ops.gr.init.enable_mme_config_ptimer(g, gr_ctx));
if (err != 0) {
nvgpu_err(g, "fail to enable mme_config_ptimer");
goto out;
}
}
#endif
/*
* Register init values are saved in
* gops.gr.init.capture_gfx_regs(). Update and set the values as

24
drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.c
View File

@@ -78,7 +78,31 @@ void ga10b_gr_init_commit_rops_crop_override(struct gk20a *g,
}
}
#endif
#ifdef CONFIG_NVGPU_NON_FUSA
int ga10b_gr_init_enable_mme_config_ptimer(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx)
{
u32 reg_val;
nvgpu_gr_ctx_patch_write_begin(g, gr_ctx, true);
reg_val = nvgpu_readl(g, gr_pri_mme_config_r());
reg_val = set_field(reg_val,
gr_pri_mme_config_config_ptimer_m(),
gr_pri_mme_config_config_ptimer_enable_f());
nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_pri_mme_config_r(),
reg_val, true);
reg_val = nvgpu_readl(g, gr_pri_mme_fe1_config_r());
reg_val = set_field(reg_val,
gr_pri_mme_fe1_config_config_fe1_ptimer_m(),
gr_pri_mme_fe1_config_config_fe1_ptimer_enable_f());
nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_pri_mme_fe1_config_r(),
reg_val, true);
nvgpu_gr_ctx_patch_write_end(g, gr_ctx, true);
return 0;
}
#endif
#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
void ga10b_gr_init_get_access_map(struct gk20a *g,
u32 **whitelist, u32 *num_entries)

6
drivers/gpu/nvgpu/hal/gr/init/gr_init_ga10b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -78,6 +78,10 @@ int ga10b_gr_init_wait_idle(struct gk20a *g);
void ga10b_gr_init_eng_config(struct gk20a *g);
int ga10b_gr_init_reset_gpcs(struct gk20a *g);
int ga10b_gr_init_wait_empty(struct gk20a *g);
#ifdef CONFIG_NVGPU_NON_FUSA
int ga10b_gr_init_enable_mme_config_ptimer(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx);
#endif
#ifndef CONFIG_NVGPU_NON_FUSA
void ga10b_gr_init_set_default_compute_regs(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx);

3
drivers/gpu/nvgpu/hal/init/hal_ga10b.c
View File

@@ -649,6 +649,9 @@ static const struct gops_gr_init ga10b_ops_gr_init = {
.commit_global_attrib_cb = gv11b_gr_init_commit_global_attrib_cb,
.commit_global_cb_manager = gp10b_gr_init_commit_global_cb_manager,
.pipe_mode_override = gm20b_gr_init_pipe_mode_override,
#ifdef CONFIG_NVGPU_NON_FUSA
.enable_mme_config_ptimer = ga10b_gr_init_enable_mme_config_ptimer,
#endif
#ifdef CONFIG_NVGPU_GR_GOLDEN_CTX_VERIFICATION
.load_sw_bundle_init = gv11b_gr_init_load_sw_bundle_init,
#else

4
drivers/gpu/nvgpu/include/nvgpu/gops/gr.h
View File

@@ -856,6 +856,10 @@ struct gops_gr_init {
struct nvgpu_gr_ctx *gr_ctx,
bool patch);
void (*pipe_mode_override)(struct gk20a *g, bool enable);
#ifdef CONFIG_NVGPU_NON_FUSA
int (*enable_mme_config_ptimer)(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx);
#endif
void (*commit_ctxsw_spill)(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx,
u64 addr, u32 size, bool patch);

6
drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_gr_ga10b.h
View File

@@ -445,6 +445,12 @@
#define gr_pri_mme_shadow_ram_index_nvclass_v(r) (((r) >> 0U) & 0xffffU)
#define gr_pri_mme_shadow_ram_index_write_trigger_f() (0x80000000U)
#define gr_pri_mme_shadow_ram_data_r() (0x0040448cU)
#define gr_pri_mme_config_r() (0x00404498U)
#define gr_pri_mme_config_config_ptimer_m() (U32(0x1U) << 1U)
#define gr_pri_mme_config_config_ptimer_enable_f() (0x2U)
#define gr_pri_mme_fe1_config_r() (0x0040a798U)
#define gr_pri_mme_fe1_config_config_fe1_ptimer_m() (U32(0x1U) << 1U)
#define gr_pri_mme_fe1_config_config_fe1_ptimer_enable_f() (0x2U)
#define gr_mme_hww_esr_r() (0x00404490U)
#define gr_mme_hww_esr_reset_active_f() (0x40000000U)
#define gr_mme_hww_esr_en_enable_f() (0x80000000U)