gpu: nvgpu: Add support for gm204 and gm206

Add support for chips gm204 and gm206. Adds also support for reading
VBIOS and booting devinit and pre-os images on PMU.

Change-Id: I4824b44245611e5379ace62793cc37158048f432
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1120467
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ken Adams <kadams@nvidia.com>

drivers/gpu/nvgpu/Makefile

@@ -73,7 +73,12 @@ nvgpu-y := \
 	gm20b/mc_gm20b.o \
 	gm20b/debug_gm20b.o \
 	gm20b/cde_gm20b.o \
-	gm20b/therm_gm20b.o
+	gm20b/therm_gm20b.o \
+	gm206/bios_gm206.o \
+	gm206/fifo_gm206.o \
+	gm206/hal_gm206.o \
+	gm206/gr_gm206.o
+
 nvgpu-$(CONFIG_TEGRA_GK20A) += gk20a/platform_gk20a_tegra.o
 nvgpu-$(CONFIG_SYNC) += gk20a/sync_gk20a.o
 nvgpu-$(CONFIG_GK20A_PCI) += pci.o

drivers/gpu/nvgpu/gk20a/gk20a.c

@@ -792,6 +792,11 @@ int gk20a_pm_finalize_poweron(struct device *dev)
 	if (err)
 		goto done;
 
+	if (g->ops.bios.init)
+		err = g->ops.bios.init(g);
+	if (err)
+		goto done;
+
 	if (!tegra_platform_is_silicon())
 		gk20a_writel(g, bus_intr_en_0_r(), 0x0);
 	else

drivers/gpu/nvgpu/gk20a/gk20a.h

@@ -592,6 +592,40 @@ struct gpu_ops {
 
 	int (*get_litter_value)(struct gk20a *g, enum nvgpu_litter_value value);
 	int (*chip_init_gpu_characteristics)(struct gk20a *g);
+
+	struct {
+		int (*init)(struct gk20a *g);
+	} bios;
+};
+
+struct nvgpu_bios_ucode {
+	u8 *bootloader;
+	u32 bootloader_phys_base;
+	u32 bootloader_size;
+	u8 *ucode;
+	u32 phys_base;
+	u32 size;
+	u8 *dmem;
+	u32 dmem_phys_base;
+	u32 dmem_size;
+	u32 code_entry_point;
+};
+
+struct nvgpu_bios {
+	u8 *data;
+
+	struct nvgpu_bios_ucode devinit;
+	struct nvgpu_bios_ucode preos;
+
+	u8 *devinit_tables;
+	u32 devinit_tables_size;
+	u8 *bootscripts;
+	u32 bootscripts_size;
+
+	u32 devinit_tables_phys_base;
+	u32 devinit_script_phys_base;
+
+	u32 expansion_rom_offset;
 };
 
 struct gk20a {
@@ -763,6 +797,9 @@ struct gk20a {
 	bool mmu_debug_ctrl;
 
 	u32 tpc_fs_mask_user;
+
+	struct nvgpu_bios bios;
+	struct debugfs_blob_wrapper bios_blob;
 };
 
 static inline unsigned long gk20a_get_gr_idle_timeout(struct gk20a *g)
@@ -1020,6 +1057,12 @@ gk20a_request_firmware(struct gk20a *g, const char *fw_name);
 #define GK20A_GPUID_GM20B \
 	GK20A_GPUID(NVGPU_GPU_ARCH_GM200, NVGPU_GPU_IMPL_GM20B)
 
+#define GK20A_GPUID_GM204 \
+	GK20A_GPUID(NVGPU_GPU_ARCH_GM200, NVGPU_GPU_IMPL_GM204)
+
+#define GK20A_GPUID_GM206 \
+	GK20A_GPUID(NVGPU_GPU_ARCH_GM200, NVGPU_GPU_IMPL_GM206)
+
 int gk20a_init_gpu_characteristics(struct gk20a *g);
 
 void gk20a_pbus_isr(struct gk20a *g);

drivers/gpu/nvgpu/gk20a/hal.c

@@ -16,6 +16,7 @@
 #include "gk20a.h"
 #include "hal_gk20a.h"
 #include "gm20b/hal_gm20b.h"
+#include "gm206/hal_gm206.h"
 
 #ifdef CONFIG_ARCH_TEGRA_18x_SOC
 #include "nvgpu_gpuid_t18x.h"
@@ -38,11 +39,21 @@ int gpu_init_hal(struct gk20a *g)
 		if (gm20b_init_hal(g))
 			return -ENODEV;
 		break;
+	case GK20A_GPUID_GM204:
+	case GK20A_GPUID_GM206:
+		gk20a_dbg_info("gm20x detected");
+		if (gm206_init_hal(g))
+			return -ENODEV;
+		break;
 #if defined(CONFIG_ARCH_TEGRA_18x_SOC)
 	case TEGRA_18x_GPUID:
 		if (TEGRA_18x_GPUID_HAL(g))
 			return -ENODEV;
 		break;
+	case TEGRA_18x_GPUID2:
+		if (TEGRA_18x_GPUID2_HAL(g))
+			return -ENODEV;
+		break;
 #endif
 #if defined(CONFIG_ARCH_TEGRA_19x_SOC)
 	case TEGRA_19x_GPUID:

drivers/gpu/nvgpu/gm206/bios_gm206.c

@@ -0,0 +1,718 @@
+/*
+ * Copyright (c) 2015-2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/types.h>
+
+#include "gk20a/gk20a.h"
+#include "gm20b/fifo_gm20b.h"
+#include "fifo_gm206.h"
+#include "hw_pwr_gm206.h"
+#include "hw_mc_gm206.h"
+#include "hw_xve_gm206.h"
+#include "hw_top_gm206.h"
+
+#define BIT_HEADER_ID 0xb8ff
+#define BIT_HEADER_SIGNATURE 0x00544942
+#define BIOS_SIZE 0x40000
+#define NV_PCFG 0x88000
+#define PMU_BOOT_TIMEOUT_DEFAULT	100 /* usec */
+#define PMU_BOOT_TIMEOUT_MAX		2000000 /* usec */
+
+static u16 gm206_bios_rdu16(struct gk20a *g, int offset)
+{
+	u16 val = (g->bios.data[offset+1] << 8) + g->bios.data[offset];
+	return val;
+}
+
+static u32 gm206_bios_rdu32(struct gk20a *g, int offset)
+{
+	u32 val = (g->bios.data[offset+3] << 24) +
+		  (g->bios.data[offset+2] << 16) +
+		  (g->bios.data[offset+1] << 8) +
+		  g->bios.data[offset];
+	return val;
+}
+
+struct bit {
+	u16 id;
+	u32 signature;
+	u16 bcd_version;
+	u8 header_size;
+	u8 token_size;
+	u8 token_entries;
+	u8 header_checksum;
+} __packed;
+
+struct bit_token {
+	u8 token_id;
+	u8 data_version;
+	u16 data_size;
+	u16 data_ptr;
+} __packed;
+
+#define TOKEN_ID_NVINIT_PTRS 0x49
+#define TOKEN_ID_FALCON_DATA 0x70
+
+struct nvinit_ptrs {
+	u16 initscript_table_ptr;
+	u16 macro_index_table_ptr;
+	u16 macro_table_ptr;
+	u16 condition_table_ptr;
+	u16 io_condition_table_ptr;
+	u16 io_flag_condition_table_ptr;
+	u16 init_function_table_ptr;
+	u16 vbios_private_table_ptr;
+	u16 data_arrays_table_ptr;
+	u16 pcie_settings_script_ptr;
+	u16 devinit_tables_ptr;
+	u16 devinit_tables_size;
+	u16 bootscripts_ptr;
+	u16 bootscripts_size;
+	u16 nvlink_config_data_ptr;
+} __packed;
+
+struct falcon_data_v2 {
+	u32 falcon_ucode_table_ptr;
+} __packed;
+
+struct falcon_ucode_table_hdr_v1 {
+	u8 version;
+	u8 header_size;
+	u8 entry_size;
+	u8 entry_count;
+	u8 desc_version;
+	u8 desc_size;
+} __packed;
+
+struct falcon_ucode_table_entry_v1 {
+	u8 application_id;
+	u8 target_id;
+	u32 desc_ptr;
+} __packed;
+
+#define TARGET_ID_PMU 0x01
+#define APPLICATION_ID_DEVINIT 0x04
+#define APPLICATION_ID_PRE_OS 0x01
+
+struct falcon_ucode_desc_v1 {
+	union {
+		u32 v_desc;
+		u32 stored_size;
+	} hdr_size;
+	u32 uncompressed_size;
+	u32 virtual_entry;
+	u32 interface_offset;
+	u32 imem_phys_base;
+	u32 imem_load_size;
+	u32 imem_virt_base;
+	u32 imem_sec_base;
+	u32 imem_sec_size;
+	u32 dmem_offset;
+	u32 dmem_phys_base;
+	u32 dmem_load_size;
+} __packed;
+
+struct application_interface_table_hdr_v1 {
+	u8 version;
+	u8 header_size;
+	u8 entry_size;
+	u8 entry_count;
+} __packed;
+
+struct application_interface_entry_v1 {
+	u32 id;
+	u32 dmem_offset;
+} __packed;
+
+#define APPINFO_ID_DEVINIT 0x01
+
+struct devinit_engine_interface {
+	u32 field0;
+	u32 field1;
+	u32 tables_phys_base;
+	u32 tables_virt_base;
+	u32 script_phys_base;
+	u32 script_virt_base;
+	u32 script_virt_entry;
+	u16 script_size;
+	u8 memory_strap_count;
+	u8 reserved;
+	u32 memory_information_table_virt_base;
+	u32 empty_script_virt_base;
+	u32 cond_table_virt_base;
+	u32 io_cond_table_virt_base;
+	u32 data_arrays_table_virt_base;
+	u32 gpio_assignment_table_virt_base;
+} __packed;
+
+struct pci_exp_rom {
+	u16 sig;
+	u8 reserved[0x16];
+	u16 pci_data_struct_ptr;
+	u32 size_of_block;
+} __packed;
+
+struct pci_data_struct {
+	u32 sig;
+	u16 vendor_id;
+	u16 device_id;
+	u16 device_list_ptr;
+	u16 pci_data_struct_len;
+	u8 pci_data_struct_rev;
+	u8 class_code[3];
+	u16 image_len;
+	u16 vendor_rom_rev;
+	u8 code_type;
+	u8 last_image;
+	u16 max_runtime_image_len;
+} __packed;
+
+struct pci_ext_data_struct {
+	u32 sig;
+	u16 nv_pci_data_ext_rev;
+	u16 nv_pci_data_ext_len;
+	u16 sub_image_len;
+	u8 priv_last_image;
+	u8 flags;
+} __packed;
+
+static void gm206_bios_parse_rom(struct gk20a *g)
+{
+	int offset = 0;
+	int last = 0;
+
+	while (!last) {
+		struct pci_exp_rom *pci_rom;
+		struct pci_data_struct *pci_data;
+		struct pci_ext_data_struct *pci_ext_data;
+
+		pci_rom = (struct pci_exp_rom *)&g->bios.data[offset];
+		gk20a_dbg_fn("pci rom sig %04x ptr %04x block %x",
+				pci_rom->sig, pci_rom->pci_data_struct_ptr,
+				pci_rom->size_of_block);
+
+		pci_data =
+			(struct pci_data_struct *)
+			&g->bios.data[offset + pci_rom->pci_data_struct_ptr];
+		gk20a_dbg_fn("pci data sig %08x len %d image len %x type %x last %d max %08x",
+				pci_data->sig, pci_data->pci_data_struct_len,
+				pci_data->image_len, pci_data->code_type,
+				pci_data->last_image,
+				pci_data->max_runtime_image_len);
+
+		if (pci_data->code_type == 0x3) {
+			pci_ext_data = (struct pci_ext_data_struct *)
+				&g->bios.data[(offset +
+					       pci_rom->pci_data_struct_ptr +
+					       pci_data->pci_data_struct_len +
+					       0xf)
+					      & ~0xf];
+			gk20a_dbg_fn("pci ext data sig %08x rev %x len %x sub_image_len %x priv_last %d flags %x",
+					pci_ext_data->sig,
+					pci_ext_data->nv_pci_data_ext_rev,
+					pci_ext_data->nv_pci_data_ext_len,
+					pci_ext_data->sub_image_len,
+					pci_ext_data->priv_last_image,
+					pci_ext_data->flags);
+
+			gk20a_dbg_fn("expansion rom offset %x",
+					pci_data->image_len * 512);
+			g->bios.expansion_rom_offset =
+				pci_data->image_len * 512;
+			offset += pci_ext_data->sub_image_len * 512;
+			last = pci_ext_data->priv_last_image;
+		} else {
+			offset += pci_data->image_len * 512;
+			last = pci_data->last_image;
+		}
+	}
+}
+
+static void gm206_bios_parse_nvinit_ptrs(struct gk20a *g, int offset)
+{
+	struct nvinit_ptrs nvinit_ptrs;
+
+	memcpy(&nvinit_ptrs, &g->bios.data[offset], sizeof(nvinit_ptrs));
+	gk20a_dbg_fn("devinit ptr %x size %d", nvinit_ptrs.devinit_tables_ptr,
+			nvinit_ptrs.devinit_tables_size);
+	gk20a_dbg_fn("bootscripts ptr %x size %d", nvinit_ptrs.bootscripts_ptr,
+			nvinit_ptrs.bootscripts_size);
+
+	g->bios.devinit_tables = &g->bios.data[nvinit_ptrs.devinit_tables_ptr];
+	g->bios.devinit_tables_size = nvinit_ptrs.devinit_tables_size;
+	g->bios.bootscripts = &g->bios.data[nvinit_ptrs.bootscripts_ptr];
+	g->bios.bootscripts_size = nvinit_ptrs.bootscripts_size;
+}
+
+static void gm206_bios_parse_devinit_appinfo(struct gk20a *g, int dmem_offset)
+{
+	struct devinit_engine_interface interface;
+
+	memcpy(&interface, &g->bios.devinit.dmem[dmem_offset], sizeof(interface));
+	gk20a_dbg_fn("devinit tables phys %x script phys %x size %d",
+			interface.tables_phys_base,
+			interface.script_phys_base,
+			interface.script_size);
+
+	g->bios.devinit_tables_phys_base = interface.tables_phys_base;
+	g->bios.devinit_script_phys_base = interface.script_phys_base;
+}
+
+static int gm206_bios_parse_appinfo_table(struct gk20a *g, int offset)
+{
+	struct application_interface_table_hdr_v1 hdr;
+	int i;
+
+	memcpy(&hdr, &g->bios.data[offset], sizeof(hdr));
+
+	gk20a_dbg_fn("appInfoHdr ver %d size %d entrySize %d entryCount %d",
+			hdr.version, hdr.header_size,
+			hdr.entry_size, hdr.entry_count);
+
+	if (hdr.version != 1)
+		return 0;
+
+	offset += sizeof(hdr);
+	for (i = 0; i < hdr.entry_count; i++) {
+		struct application_interface_entry_v1 entry;
+
+		memcpy(&entry, &g->bios.data[offset], sizeof(entry));
+
+		gk20a_dbg_fn("appInfo id %d dmem_offset %d",
+				entry.id, entry.dmem_offset);
+
+		if (entry.id == APPINFO_ID_DEVINIT)
+			gm206_bios_parse_devinit_appinfo(g, entry.dmem_offset);
+
+		offset += hdr.entry_size;
+	}
+
+	return 0;
+}
+
+static int gm206_bios_parse_falcon_ucode_desc(struct gk20a *g,
+		struct nvgpu_bios_ucode *ucode, int offset)
+{
+	struct falcon_ucode_desc_v1 desc;
+
+	memcpy(&desc, &g->bios.data[offset], sizeof(desc));
+	gk20a_dbg_info("falcon ucode desc stored size %d uncompressed size %d",
+			desc.hdr_size.stored_size, desc.uncompressed_size);
+	gk20a_dbg_info("falcon ucode desc virtualEntry %x, interfaceOffset %x",
+			desc.virtual_entry, desc.interface_offset);
+	gk20a_dbg_info("falcon ucode IMEM phys base %x, load size %x virt base %x sec base %x sec size %x",
+			desc.imem_phys_base, desc.imem_load_size,
+			desc.imem_virt_base, desc.imem_sec_base,
+			desc.imem_sec_size);
+	gk20a_dbg_info("falcon ucode DMEM offset %d phys base %x, load size %d",
+			desc.dmem_offset, desc.dmem_phys_base,
+			desc.dmem_load_size);
+
+	if (desc.hdr_size.stored_size != desc.uncompressed_size) {
+		gk20a_dbg_info("does not match");
+		return -EINVAL;
+	}
+
+	ucode->code_entry_point = desc.virtual_entry;
+	ucode->bootloader = &g->bios.data[offset] + sizeof(desc);
+	ucode->bootloader_phys_base = desc.imem_phys_base;
+	ucode->bootloader_size = desc.imem_load_size - desc.imem_sec_size;
+	ucode->ucode = ucode->bootloader + ucode->bootloader_size;
+	ucode->phys_base = ucode->bootloader_phys_base + ucode->bootloader_size;
+	ucode->size = desc.imem_sec_size;
+	ucode->dmem = ucode->bootloader + desc.dmem_offset;
+	ucode->dmem_phys_base = desc.dmem_phys_base;
+	ucode->dmem_size = desc.dmem_load_size;
+
+	return gm206_bios_parse_appinfo_table(g,
+			offset + sizeof(desc) +
+			desc.dmem_offset + desc.interface_offset);
+}
+
+static int gm206_bios_parse_falcon_ucode_table(struct gk20a *g, int offset)
+{
+	struct falcon_ucode_table_hdr_v1 hdr;
+	int i;
+
+	memcpy(&hdr, &g->bios.data[offset], sizeof(hdr));
+	gk20a_dbg_fn("falcon ucode table ver %d size %d entrySize %d entryCount %d descVer %d descSize %d",
+			hdr.version, hdr.header_size,
+			hdr.entry_size, hdr.entry_count,
+			hdr.desc_version, hdr.desc_size);
+
+	if (hdr.version != 1)
+		return -EINVAL;
+
+	offset += hdr.header_size;
+
+	for (i = 0; i < hdr.entry_count; i++) {
+		struct falcon_ucode_table_entry_v1 entry;
+
+		memcpy(&entry, &g->bios.data[offset], sizeof(entry));
+
+		gk20a_dbg_fn("falcon ucode table entry appid %x targetId %x descPtr %x",
+				entry.application_id, entry.target_id,
+				entry.desc_ptr);
+
+		if (entry.target_id == TARGET_ID_PMU &&
+		    entry.application_id == APPLICATION_ID_DEVINIT) {
+			int err;
+
+			err = gm206_bios_parse_falcon_ucode_desc(g,
+					&g->bios.devinit, entry.desc_ptr);
+			if (err)
+				err = gm206_bios_parse_falcon_ucode_desc(g,
+					&g->bios.devinit,
+					entry.desc_ptr +
+					 g->bios.expansion_rom_offset);
+
+			if (err)
+				gk20a_err(dev_from_gk20a(g),
+					  "could not parse devinit ucode desc");
+		} else if (entry.target_id == TARGET_ID_PMU &&
+		    entry.application_id == APPLICATION_ID_PRE_OS) {
+			int err;
+
+			err = gm206_bios_parse_falcon_ucode_desc(g,
+					&g->bios.preos, entry.desc_ptr);
+			if (err)
+				err = gm206_bios_parse_falcon_ucode_desc(g,
+					&g->bios.preos,
+					entry.desc_ptr +
+					 g->bios.expansion_rom_offset);
+
+			if (err)
+				gk20a_err(dev_from_gk20a(g),
+					  "could not parse preos ucode desc");
+		}
+
+		offset += hdr.entry_size;
+	}
+
+	return 0;
+}
+
+static void gm206_bios_parse_falcon_data_v2(struct gk20a *g, int offset)
+{
+	struct falcon_data_v2 falcon_data;
+	int err;
+
+	memcpy(&falcon_data, &g->bios.data[offset], sizeof(falcon_data));
+	gk20a_dbg_fn("falcon ucode table ptr %x",
+			falcon_data.falcon_ucode_table_ptr);
+	err = gm206_bios_parse_falcon_ucode_table(g,
+			falcon_data.falcon_ucode_table_ptr);
+	if (err)
+		err = gm206_bios_parse_falcon_ucode_table(g,
+				falcon_data.falcon_ucode_table_ptr +
+			g->bios.expansion_rom_offset);
+
+	if (err)
+		gk20a_err(dev_from_gk20a(g),
+			  "could not parse falcon ucode table");
+}
+
+static void gm206_bios_parse_bit(struct gk20a *g, int offset)
+{
+	struct bit bit;
+	struct bit_token bit_token;
+	int i;
+
+	gk20a_dbg_fn("");
+	memcpy(&bit, &g->bios.data[offset], sizeof(bit));
+
+	gk20a_dbg_info("BIT header: %04x %08x", bit.id, bit.signature);
+	gk20a_dbg_info("tokens: %d entries * %d bytes",
+			bit.token_entries, bit.token_size);
+
+	offset += bit.header_size;
+	for (i = 0; i < bit.token_entries; i++) {
+		memcpy(&bit_token, &g->bios.data[offset], sizeof(bit_token));
+
+		gk20a_dbg_info("BIT token id %d ptr %d size %d ver %d",
+				bit_token.token_id, bit_token.data_ptr,
+				bit_token.data_size, bit_token.data_version);
+
+		switch (bit_token.token_id) {
+		case TOKEN_ID_NVINIT_PTRS:
+			gm206_bios_parse_nvinit_ptrs(g, bit_token.data_ptr);
+			break;
+		case TOKEN_ID_FALCON_DATA:
+			if (bit_token.data_version == 2)
+				gm206_bios_parse_falcon_data_v2(g,
+						bit_token.data_ptr);
+			break;
+		default:
+			break;
+		}
+
+		offset += bit.token_size;
+	}
+	gk20a_dbg_fn("done");
+}
+
+static void upload_code(struct gk20a *g, u32 dst,
+			u8 *src, u32 size, u8 port, bool sec)
+{
+	u32 i, words;
+	u32 *src_u32 = (u32 *)src;
+	u32 blk;
+	u32 tag = 0;
+
+	gk20a_dbg_info("upload %d bytes to %x", size, dst);
+
+	words = size >> 2;
+
+	blk = dst >> 8;
+	tag = blk;
+
+	gk20a_dbg_info("upload %d words to %x block %d",
+			words, dst, blk);
+
+	gk20a_writel(g, pwr_falcon_imemc_r(port),
+		pwr_falcon_imemc_offs_f(dst >> 2) |
+		pwr_falcon_imemc_blk_f(blk) |
+		pwr_falcon_imemc_aincw_f(1) |
+		sec << 28);
+
+	for (i = 0; i < words; i++) {
+		if (i % 64 == 0) {
+			gk20a_writel(g, 0x10a188, tag);
+			tag++;
+		}
+
+		gk20a_writel(g, pwr_falcon_imemd_r(port), src_u32[i]);
+	}
+
+	while (i % 64) {
+		gk20a_writel(g, pwr_falcon_imemd_r(port), 0);
+		i++;
+	}
+}
+
+static void upload_data(struct gk20a *g, u32 dst, u8 *src, u32 size, u8 port)
+{
+	u32 i, words;
+	u32 *src_u32 = (u32 *)src;
+	u32 blk;
+
+	gk20a_dbg_info("upload %d bytes to %x", size, dst);
+
+	words = DIV_ROUND_UP(size, 4);
+
+	blk = dst >> 8;
+
+	gk20a_dbg_info("upload %d words to %x blk %d",
+			words, dst, blk);
+	gk20a_writel(g, pwr_falcon_dmemc_r(port),
+		pwr_falcon_dmemc_offs_f(dst >> 2) |
+		pwr_falcon_dmemc_blk_f(blk) |
+		pwr_falcon_dmemc_aincw_f(1));
+
+	for (i = 0; i < words; i++)
+		gk20a_writel(g, pwr_falcon_dmemd_r(port), src_u32[i]);
+}
+
+static int gm206_bios_devinit(struct gk20a *g)
+{
+	int retries = PMU_BOOT_TIMEOUT_MAX / PMU_BOOT_TIMEOUT_DEFAULT;
+	int err = 0;
+	int val;
+
+	gk20a_dbg_fn("");
+	g->ops.pmu.reset(g);
+
+	do {
+		u32 w = gk20a_readl(g, pwr_falcon_dmactl_r()) &
+			(pwr_falcon_dmactl_dmem_scrubbing_m() |
+			 pwr_falcon_dmactl_imem_scrubbing_m());
+
+		if (!w) {
+			gk20a_dbg_fn("done");
+			break;
+		}
+		udelay(PMU_BOOT_TIMEOUT_DEFAULT);
+	} while (--retries || !tegra_platform_is_silicon());
+
+	/*  todo check retries */
+	upload_code(g, g->bios.devinit.bootloader_phys_base,
+			g->bios.devinit.bootloader,
+			g->bios.devinit.bootloader_size,
+			0, 0);
+	upload_code(g, g->bios.devinit.phys_base,
+			g->bios.devinit.ucode,
+			g->bios.devinit.size,
+			0, 1);
+	upload_data(g, g->bios.devinit.dmem_phys_base,
+			g->bios.devinit.dmem,
+			g->bios.devinit.dmem_size,
+			0);
+	upload_data(g, g->bios.devinit_tables_phys_base,
+			g->bios.devinit_tables,
+			g->bios.devinit_tables_size,
+			0);
+	upload_data(g, g->bios.devinit_script_phys_base,
+			g->bios.bootscripts,
+			g->bios.bootscripts_size,
+			0);
+
+	gk20a_writel(g, pwr_falcon_bootvec_r(),
+		pwr_falcon_bootvec_vec_f(g->bios.devinit.code_entry_point));
+	gk20a_writel(g, pwr_falcon_dmactl_r(),
+			pwr_falcon_dmactl_require_ctx_f(0));
+	gk20a_writel(g, pwr_falcon_cpuctl_r(),
+		pwr_falcon_cpuctl_startcpu_f(1));
+
+	retries = PMU_BOOT_TIMEOUT_MAX / PMU_BOOT_TIMEOUT_DEFAULT;
+	do {
+		val = top_scratch1_devinit_completed_v(
+				gk20a_readl(g, top_scratch1_r()));
+		udelay(PMU_BOOT_TIMEOUT_DEFAULT);
+	} while (!val && retries--);
+
+	gk20a_writel(g, pwr_falcon_irqsclr_r(),
+	     pwr_falcon_irqstat_halt_true_f());
+	gk20a_readl(g, pwr_falcon_irqsclr_r());
+
+	if (!retries)
+		err = -EINVAL;
+
+	gk20a_dbg_fn("done");
+	return err;
+}
+
+static int gm206_bios_preos(struct gk20a *g)
+{
+	int retries = GR_IDLE_CHECK_MAX / GR_IDLE_CHECK_DEFAULT;
+	int err = 0;
+	int val;
+
+	gk20a_dbg_fn("");
+	g->ops.pmu.reset(g);
+
+	do {
+		u32 w = gk20a_readl(g, pwr_falcon_dmactl_r()) &
+			(pwr_falcon_dmactl_dmem_scrubbing_m() |
+			 pwr_falcon_dmactl_imem_scrubbing_m());
+
+		if (!w) {
+			gk20a_dbg_fn("done");
+			break;
+		}
+		udelay(GR_IDLE_CHECK_DEFAULT);
+	} while (--retries || !tegra_platform_is_silicon());
+
+	/*  todo check retries */
+	upload_code(g, g->bios.preos.bootloader_phys_base,
+			g->bios.preos.bootloader,
+			g->bios.preos.bootloader_size,
+			0, 0);
+	upload_code(g, g->bios.preos.phys_base,
+			g->bios.preos.ucode,
+			g->bios.preos.size,
+			0, 1);
+	upload_data(g, g->bios.preos.dmem_phys_base,
+			g->bios.preos.dmem,
+			g->bios.preos.dmem_size,
+			0);
+
+	gk20a_writel(g, pwr_falcon_bootvec_r(),
+		pwr_falcon_bootvec_vec_f(g->bios.preos.code_entry_point));
+	gk20a_writel(g, pwr_falcon_dmactl_r(),
+			pwr_falcon_dmactl_require_ctx_f(0));
+	gk20a_writel(g, pwr_falcon_cpuctl_r(),
+		pwr_falcon_cpuctl_startcpu_f(1));
+
+	retries = PMU_BOOT_TIMEOUT_MAX / PMU_BOOT_TIMEOUT_DEFAULT;
+	do {
+		val = pwr_falcon_cpuctl_halt_intr_v(
+				gk20a_readl(g, pwr_falcon_cpuctl_r()));
+		udelay(PMU_BOOT_TIMEOUT_DEFAULT);
+	} while (!val && retries--);
+
+	gk20a_writel(g, pwr_falcon_irqsclr_r(),
+	     pwr_falcon_irqstat_halt_true_f());
+	gk20a_readl(g, pwr_falcon_irqsclr_r());
+
+	if (!retries)
+		err = -EINVAL;
+
+	gk20a_dbg_fn("done");
+	return err;
+}
+
+static int gm206_bios_init(struct gk20a *g)
+{
+	int i;
+	struct gk20a_platform *platform = dev_get_drvdata(g->dev);
+	struct dentry *d;
+	int err;
+
+	gk20a_dbg_fn("");
+	g->bios.data = kzalloc(BIOS_SIZE, GFP_KERNEL);
+	if (!g->bios.data)
+		return -ENOMEM;
+
+	gk20a_dbg_info("reading bios");
+	gk20a_writel(g, NV_PCFG + xve_rom_ctrl_r(),
+			xve_rom_ctrl_rom_shadow_disabled_f());
+	for (i = 0; i < BIOS_SIZE/4; i++) {
+		u32 val = be32_to_cpu(gk20a_readl(g, 0x300000 + i*4));
+
+		g->bios.data[(i*4)] = (val >> 24) & 0xff;
+		g->bios.data[(i*4)+1] = (val >> 16) & 0xff;
+		g->bios.data[(i*4)+2] = (val >> 8) & 0xff;
+		g->bios.data[(i*4)+3] = val & 0xff;
+	}
+	gk20a_writel(g, NV_PCFG + xve_rom_ctrl_r(),
+			xve_rom_ctrl_rom_shadow_enabled_f());
+
+	gm206_bios_parse_rom(g);
+	gk20a_dbg_info("read bios");
+	for (i = 0; i < BIOS_SIZE; i++) {
+		if (gm206_bios_rdu16(g, i) == BIT_HEADER_ID &&
+		    gm206_bios_rdu32(g, i+2) ==  BIT_HEADER_SIGNATURE) {
+			gm206_bios_parse_bit(g, i);
+		}
+	}
+
+	g->bios_blob.data = g->bios.data;
+	g->bios_blob.size = BIOS_SIZE;
+
+	d = debugfs_create_blob("bios", S_IRUGO, platform->debugfs,
+			&g->bios_blob);
+	if (!d)
+		gk20a_err(g->dev, "No debugfs?");
+
+	gk20a_dbg_fn("done");
+
+	err = gm206_bios_devinit(g);
+	if (err) {
+		gk20a_err(g->dev, "devinit failed");
+		return err;
+	}
+
+	err = gm206_bios_preos(g);
+	if (err) {
+		gk20a_err(g->dev, "pre-os failed");
+		return err;
+	}
+
+	return 0;
+}
+
+void gm206_init_bios(struct gpu_ops *gops)
+{
+	gops->bios.init = gm206_bios_init;
+}

drivers/gpu/nvgpu/gm206/bios_gm206.h

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef NVGPU_BIOS_GM206_H
+#define NVGPU_BIOS_GM206_H
+struct gpu_ops;
+
+void gm206_init_bios(struct gpu_ops *gops);
+#endif

drivers/gpu/nvgpu/gm206/fifo_gm206.c

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2015-2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/types.h>
+
+#include "gk20a/gk20a.h"
+#include "gm20b/fifo_gm20b.h"
+#include "fifo_gm206.h"
+#include "hw_ccsr_gm206.h"
+
+static u32 gm206_fifo_get_num_fifos(struct gk20a *g)
+{
+	return ccsr_channel__size_1_v();
+}
+
+void gm206_init_fifo(struct gpu_ops *gops)
+{
+	gm20b_init_fifo(gops);
+	gops->fifo.get_num_fifos = gm206_fifo_get_num_fifos;
+}

drivers/gpu/nvgpu/gm206/fifo_gm206.h

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef NVGPU_FIFO_GM206_H
+#define NVGPU_FIFO_GM206_H
+struct gpu_ops;
+void gm206_init_fifo(struct gpu_ops *gops);
+#endif

drivers/gpu/nvgpu/gm206/gr_gm206.c

@@ -0,0 +1,92 @@
+/*
+ * gm206 GR
+ *
+ * Copyright (c) 2011-2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/types.h>
+#include <linux/delay.h>	/* for mdelay */
+#include <linux/io.h>
+#include <linux/tegra-fuse.h>
+#include <linux/vmalloc.h>
+
+#include "gk20a/gk20a.h"
+
+#include "gm20b/gr_gm20b.h"
+#include "gr_gm206.h"
+#include "hw_fb_gm206.h"
+#include "hw_gr_gm206.h"
+
+static void gr_gm206_init_gpc_mmu(struct gk20a *g)
+{
+	u32 temp;
+
+	gk20a_dbg_info("initialize gpc mmu");
+
+	temp = gk20a_readl(g, fb_mmu_ctrl_r());
+	temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() |
+		gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() |
+		gr_gpcs_pri_mmu_ctrl_use_full_comp_tag_line_m() |
+		gr_gpcs_pri_mmu_ctrl_vol_fault_m() |
+		gr_gpcs_pri_mmu_ctrl_comp_fault_m() |
+		gr_gpcs_pri_mmu_ctrl_miss_gran_m() |
+		gr_gpcs_pri_mmu_ctrl_cache_mode_m() |
+		gr_gpcs_pri_mmu_ctrl_mmu_aperture_m() |
+		gr_gpcs_pri_mmu_ctrl_mmu_vol_m() |
+		gr_gpcs_pri_mmu_ctrl_mmu_disable_m();
+	gk20a_writel(g, gr_gpcs_pri_mmu_ctrl_r(), temp);
+	gk20a_writel(g, gr_gpcs_pri_mmu_pm_unit_mask_r(), 0);
+	gk20a_writel(g, gr_gpcs_pri_mmu_pm_req_mask_r(), 0);
+
+	gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(),
+			gk20a_readl(g, fb_mmu_debug_ctrl_r()));
+	gk20a_writel(g, gr_gpcs_pri_mmu_debug_wr_r(),
+			gk20a_readl(g, fb_mmu_debug_wr_r()));
+	gk20a_writel(g, gr_gpcs_pri_mmu_debug_rd_r(),
+			gk20a_readl(g, fb_mmu_debug_rd_r()));
+
+	gk20a_writel(g, gr_gpcs_mmu_num_active_ltcs_r(),
+		gk20a_readl(g, fb_fbhub_num_active_ltcs_r()));
+	/*  TODO: num_active_ltcs2! */
+	gk20a_writel(g, 0x50833c, gk20a_readl(g, 0x100804));
+}
+
+static void gr_gm206_bundle_cb_defaults(struct gk20a *g)
+{
+	struct gr_gk20a *gr = &g->gr;
+
+	gr->bundle_cb_default_size =
+		gr_scc_bundle_cb_size_div_256b__prod_v();
+	gr->min_gpm_fifo_depth =
+		gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v();
+	gr->bundle_cb_token_limit =
+		gr_pd_ab_dist_cfg2_token_limit_init_v();
+}
+
+static void gr_gm206_cb_size_default(struct gk20a *g)
+{
+	struct gr_gk20a *gr = &g->gr;
+
+	if (!gr->attrib_cb_default_size)
+		gr->attrib_cb_default_size =
+			gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v();
+	gr->alpha_cb_default_size =
+		gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v();
+}
+
+void gm206_init_gr(struct gpu_ops *gops)
+{
+	gm20b_init_gr(gops);
+	gops->gr.init_gpc_mmu = gr_gm206_init_gpc_mmu;
+	gops->gr.bundle_cb_defaults = gr_gm206_bundle_cb_defaults;
+	gops->gr.cb_size_default = gr_gm206_cb_size_default;
+}

drivers/gpu/nvgpu/gm206/gr_gm206.h

@@ -0,0 +1,23 @@
+/*
+ * GM206 GR
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef _NVGPU_GM206_GR_H
+#define _NVGPU_GM206_GR_H
+
+struct gpu_ops;
+
+void gm206_init_gr(struct gpu_ops *gops);
+
+#endif

drivers/gpu/nvgpu/gm206/hal_gm206.c

@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/types.h>
+#include <linux/printk.h>
+
+#include <linux/types.h>
+
+#include "gk20a/gk20a.h"
+
+#include "gm20b/mc_gm20b.h"
+#include "gm20b/ltc_gm20b.h"
+#include "gm20b/mm_gm20b.h"
+#include "gm20b/ce2_gm20b.h"
+#include "gm20b/fb_gm20b.h"
+#include "gm20b/pmu_gm20b.h"
+#include "gm20b/gr_gm20b.h"
+#include "gm20b/gr_ctx_gm20b.h"
+#include "gm20b/gm20b_gating_reglist.h"
+#include "gm20b/regops_gm20b.h"
+#include "gm20b/cde_gm20b.h"
+#include "gm20b/therm_gm20b.h"
+#include "gm20b/clk_gm20b.h"
+#include "gm20b/debug_gm20b.h"
+
+#include "fifo_gm206.h"
+#include "bios_gm206.h"
+#include "gr_gm206.h"
+#include "hw_proj_gm206.h"
+
+static struct gpu_ops gm206_ops = {
+	.clock_gating = {
+		.slcg_bus_load_gating_prod =
+			gm20b_slcg_bus_load_gating_prod,
+		.slcg_ce2_load_gating_prod =
+			gm20b_slcg_ce2_load_gating_prod,
+		.slcg_chiplet_load_gating_prod =
+			gm20b_slcg_chiplet_load_gating_prod,
+		.slcg_ctxsw_firmware_load_gating_prod =
+			gm20b_slcg_ctxsw_firmware_load_gating_prod,
+		.slcg_fb_load_gating_prod =
+			gm20b_slcg_fb_load_gating_prod,
+		.slcg_fifo_load_gating_prod =
+			gm20b_slcg_fifo_load_gating_prod,
+		.slcg_gr_load_gating_prod =
+			gr_gm20b_slcg_gr_load_gating_prod,
+		.slcg_ltc_load_gating_prod =
+			ltc_gm20b_slcg_ltc_load_gating_prod,
+		.slcg_perf_load_gating_prod =
+			gm20b_slcg_perf_load_gating_prod,
+		.slcg_priring_load_gating_prod =
+			gm20b_slcg_priring_load_gating_prod,
+		.slcg_pmu_load_gating_prod =
+			gm20b_slcg_pmu_load_gating_prod,
+		.slcg_therm_load_gating_prod =
+			gm20b_slcg_therm_load_gating_prod,
+		.slcg_xbar_load_gating_prod =
+			gm20b_slcg_xbar_load_gating_prod,
+		.blcg_bus_load_gating_prod =
+			gm20b_blcg_bus_load_gating_prod,
+		.blcg_ctxsw_firmware_load_gating_prod =
+			gm20b_blcg_ctxsw_firmware_load_gating_prod,
+		.blcg_fb_load_gating_prod =
+			gm20b_blcg_fb_load_gating_prod,
+		.blcg_fifo_load_gating_prod =
+			gm20b_blcg_fifo_load_gating_prod,
+		.blcg_gr_load_gating_prod =
+			gm20b_blcg_gr_load_gating_prod,
+		.blcg_ltc_load_gating_prod =
+			gm20b_blcg_ltc_load_gating_prod,
+		.blcg_pwr_csb_load_gating_prod =
+			gm20b_blcg_pwr_csb_load_gating_prod,
+		.blcg_pmu_load_gating_prod =
+			gm20b_blcg_pmu_load_gating_prod,
+		.blcg_xbar_load_gating_prod =
+			gm20b_blcg_xbar_load_gating_prod,
+		.pg_gr_load_gating_prod =
+			gr_gm20b_pg_gr_load_gating_prod,
+	}
+};
+
+static int gm206_get_litter_value(struct gk20a *g,
+		enum nvgpu_litter_value value)
+{
+	int ret = -EINVAL;
+
+	switch (value) {
+	case GPU_LIT_NUM_GPCS:
+		ret = proj_scal_litter_num_gpcs_v();
+		break;
+	case GPU_LIT_NUM_PES_PER_GPC:
+		ret = proj_scal_litter_num_pes_per_gpc_v();
+		break;
+	case GPU_LIT_NUM_ZCULL_BANKS:
+		ret = proj_scal_litter_num_zcull_banks_v();
+		break;
+	case GPU_LIT_NUM_TPC_PER_GPC:
+		ret = proj_scal_litter_num_tpc_per_gpc_v();
+		break;
+	case GPU_LIT_NUM_FBPS:
+		ret = proj_scal_litter_num_fbps_v();
+		break;
+	case GPU_LIT_GPC_BASE:
+		ret = proj_gpc_base_v();
+		break;
+	case GPU_LIT_GPC_STRIDE:
+		ret = proj_gpc_stride_v();
+		break;
+	case GPU_LIT_GPC_SHARED_BASE:
+		ret = proj_gpc_shared_base_v();
+		break;
+	case GPU_LIT_TPC_IN_GPC_BASE:
+		ret = proj_tpc_in_gpc_base_v();
+		break;
+	case GPU_LIT_TPC_IN_GPC_STRIDE:
+		ret = proj_tpc_in_gpc_stride_v();
+		break;
+	case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
+		ret = proj_tpc_in_gpc_shared_base_v();
+		break;
+	case GPU_LIT_PPC_IN_GPC_STRIDE:
+		ret = proj_ppc_in_gpc_stride_v();
+		break;
+	case GPU_LIT_ROP_BASE:
+		ret = proj_rop_base_v();
+		break;
+	case GPU_LIT_ROP_STRIDE:
+		ret = proj_rop_stride_v();
+		break;
+	case GPU_LIT_ROP_SHARED_BASE:
+		ret = proj_rop_shared_base_v();
+		break;
+	case GPU_LIT_HOST_NUM_PBDMA:
+		ret = proj_host_num_pbdma_v();
+		break;
+	case GPU_LIT_LTC_STRIDE:
+		ret = proj_ltc_stride_v();
+		break;
+	case GPU_LIT_LTS_STRIDE:
+		ret = proj_lts_stride_v();
+		break;
+	case GPU_LIT_NUM_FBPAS:
+		ret = proj_scal_litter_num_fbpas_v();
+		break;
+	case GPU_LIT_FBPA_STRIDE:
+		ret = proj_fbpa_stride_v();
+		break;
+	default:
+		BUG();
+		break;
+	}
+
+	return ret;
+}
+
+int gm206_init_hal(struct gk20a *g)
+{
+	struct gpu_ops *gops = &g->ops;
+	struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
+
+	*gops = gm206_ops;
+
+	gops->privsecurity = 0;
+	gops->securegpccs = 0;
+
+	gm20b_init_mc(gops);
+	gm20b_init_ltc(gops);
+	gm206_init_gr(gops);
+	gm20b_init_ltc(gops);
+	gm20b_init_fb(gops);
+	g->ops.fb.set_use_full_comp_tag_line = NULL;
+	gm206_init_fifo(gops);
+	gm20b_init_ce2(gops);
+	gm20b_init_gr_ctx(gops);
+	gm20b_init_mm(gops);
+	gm20b_init_pmu_ops(gops);
+	gm20b_init_clk_ops(gops);
+	gm20b_init_regops(gops);
+	gm20b_init_debug_ops(gops);
+	gm20b_init_cde_ops(gops);
+	gm20b_init_therm_ops(gops);
+	gm206_init_bios(gops);
+	gops->name = "gm206";
+	gops->chip_init_gpu_characteristics = gk20a_init_gpu_characteristics;
+	gops->get_litter_value = gm206_get_litter_value;
+	gops->gr_ctx.use_dma_for_fw_bootstrap = false;
+
+	c->twod_class = FERMI_TWOD_A;
+	c->threed_class = MAXWELL_B;
+	c->compute_class = MAXWELL_COMPUTE_B;
+	c->gpfifo_class = MAXWELL_CHANNEL_GPFIFO_A;
+	c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B;
+	c->dma_copy_class = MAXWELL_DMA_COPY_A;
+
+	return 0;
+}

drivers/gpu/nvgpu/gm206/hal_gm206.h

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef _NVGPU_HAL_GM206_H
+#define _NVGPU_HAL_GM206_H
+struct gk20a;
+
+int gm206_init_hal(struct gk20a *gops);
+#endif

drivers/gpu/nvgpu/gm206/hw_bus_gm206.h

@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_bus_gm206_h_
+#define _hw_bus_gm206_h_
+
+static inline u32 bus_bar1_block_r(void)
+{
+	return 0x00001704;
+}
+static inline u32 bus_bar1_block_ptr_f(u32 v)
+{
+	return (v & 0xfffffff) << 0;
+}
+static inline u32 bus_bar1_block_target_vid_mem_f(void)
+{
+	return 0x0;
+}
+static inline u32 bus_bar1_block_target_sys_mem_coh_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void)
+{
+	return 0x30000000;
+}
+static inline u32 bus_bar1_block_mode_virtual_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 bus_bar2_block_r(void)
+{
+	return 0x00001714;
+}
+static inline u32 bus_bar2_block_ptr_f(u32 v)
+{
+	return (v & 0xfffffff) << 0;
+}
+static inline u32 bus_bar2_block_target_vid_mem_f(void)
+{
+	return 0x0;
+}
+static inline u32 bus_bar2_block_target_sys_mem_coh_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void)
+{
+	return 0x30000000;
+}
+static inline u32 bus_bar2_block_mode_virtual_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 bus_bar1_block_ptr_shift_v(void)
+{
+	return 0x0000000c;
+}
+static inline u32 bus_bar2_block_ptr_shift_v(void)
+{
+	return 0x0000000c;
+}
+static inline u32 bus_bind_status_r(void)
+{
+	return 0x00001710;
+}
+static inline u32 bus_bind_status_bar1_pending_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 bus_bind_status_bar1_pending_empty_f(void)
+{
+	return 0x0;
+}
+static inline u32 bus_bind_status_bar1_pending_busy_f(void)
+{
+	return 0x1;
+}
+static inline u32 bus_bind_status_bar1_outstanding_v(u32 r)
+{
+	return (r >> 1) & 0x1;
+}
+static inline u32 bus_bind_status_bar1_outstanding_false_f(void)
+{
+	return 0x0;
+}
+static inline u32 bus_bind_status_bar1_outstanding_true_f(void)
+{
+	return 0x2;
+}
+static inline u32 bus_bind_status_bar2_pending_v(u32 r)
+{
+	return (r >> 2) & 0x1;
+}
+static inline u32 bus_bind_status_bar2_pending_empty_f(void)
+{
+	return 0x0;
+}
+static inline u32 bus_bind_status_bar2_pending_busy_f(void)
+{
+	return 0x4;
+}
+static inline u32 bus_bind_status_bar2_outstanding_v(u32 r)
+{
+	return (r >> 3) & 0x1;
+}
+static inline u32 bus_bind_status_bar2_outstanding_false_f(void)
+{
+	return 0x0;
+}
+static inline u32 bus_bind_status_bar2_outstanding_true_f(void)
+{
+	return 0x8;
+}
+static inline u32 bus_intr_0_r(void)
+{
+	return 0x00001100;
+}
+static inline u32 bus_intr_0_pri_squash_m(void)
+{
+	return 0x1 << 1;
+}
+static inline u32 bus_intr_0_pri_fecserr_m(void)
+{
+	return 0x1 << 2;
+}
+static inline u32 bus_intr_0_pri_timeout_m(void)
+{
+	return 0x1 << 3;
+}
+static inline u32 bus_intr_en_0_r(void)
+{
+	return 0x00001140;
+}
+static inline u32 bus_intr_en_0_pri_squash_m(void)
+{
+	return 0x1 << 1;
+}
+static inline u32 bus_intr_en_0_pri_fecserr_m(void)
+{
+	return 0x1 << 2;
+}
+static inline u32 bus_intr_en_0_pri_timeout_m(void)
+{
+	return 0x1 << 3;
+}
+#endif

drivers/gpu/nvgpu/gm206/hw_ccsr_gm206.h

@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ccsr_gm206_h_
+#define _hw_ccsr_gm206_h_
+
+static inline u32 ccsr_channel_inst_r(u32 i)
+{
+	return 0x00800000 + i*8;
+}
+static inline u32 ccsr_channel_inst__size_1_v(void)
+{
+	return 0x00001000;
+}
+static inline u32 ccsr_channel_inst_ptr_f(u32 v)
+{
+	return (v & 0xfffffff) << 0;
+}
+static inline u32 ccsr_channel_inst_target_vid_mem_f(void)
+{
+	return 0x0;
+}
+static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void)
+{
+	return 0x30000000;
+}
+static inline u32 ccsr_channel_inst_bind_false_f(void)
+{
+	return 0x0;
+}
+static inline u32 ccsr_channel_inst_bind_true_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 ccsr_channel_r(u32 i)
+{
+	return 0x00800004 + i*8;
+}
+static inline u32 ccsr_channel__size_1_v(void)
+{
+	return 0x00001000;
+}
+static inline u32 ccsr_channel_enable_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 ccsr_channel_enable_set_f(u32 v)
+{
+	return (v & 0x1) << 10;
+}
+static inline u32 ccsr_channel_enable_set_true_f(void)
+{
+	return 0x400;
+}
+static inline u32 ccsr_channel_enable_clr_true_f(void)
+{
+	return 0x800;
+}
+static inline u32 ccsr_channel_status_v(u32 r)
+{
+	return (r >> 24) & 0xf;
+}
+static inline u32 ccsr_channel_status_pending_ctx_reload_v(void)
+{
+	return 0x00000002;
+}
+static inline u32 ccsr_channel_busy_v(u32 r)
+{
+	return (r >> 28) & 0x1;
+}
+static inline u32 ccsr_channel_next_v(u32 r)
+{
+	return (r >> 1) & 0x1;
+}
+#endif

drivers/gpu/nvgpu/gm206/hw_ce2_gm206.h

@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ce2_gm206_h_
+#define _hw_ce2_gm206_h_
+
+static inline u32 ce2_intr_status_r(void)
+{
+	return 0x00106908;
+}
+static inline u32 ce2_intr_status_blockpipe_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 ce2_intr_status_blockpipe_reset_f(void)
+{
+	return 0x1;
+}
+static inline u32 ce2_intr_status_nonblockpipe_pending_f(void)
+{
+	return 0x2;
+}
+static inline u32 ce2_intr_status_nonblockpipe_reset_f(void)
+{
+	return 0x2;
+}
+static inline u32 ce2_intr_status_launcherr_pending_f(void)
+{
+	return 0x4;
+}
+static inline u32 ce2_intr_status_launcherr_reset_f(void)
+{
+	return 0x4;
+}
+#endif

drivers/gpu/nvgpu/gm206/hw_ctxsw_prog_gm206.h

@@ -0,0 +1,253 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ctxsw_prog_gm206_h_
+#define _hw_ctxsw_prog_gm206_h_
+
+static inline u32 ctxsw_prog_fecs_header_v(void)
+{
+	return 0x00000100;
+}
+static inline u32 ctxsw_prog_main_image_num_gpcs_o(void)
+{
+	return 0x00000008;
+}
+static inline u32 ctxsw_prog_main_image_patch_count_o(void)
+{
+	return 0x00000010;
+}
+static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void)
+{
+	return 0x00000014;
+}
+static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void)
+{
+	return 0x00000018;
+}
+static inline u32 ctxsw_prog_main_image_zcull_o(void)
+{
+	return 0x0000001c;
+}
+static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void)
+{
+	return 0x00000002;
+}
+static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void)
+{
+	return 0x00000020;
+}
+static inline u32 ctxsw_prog_main_image_pm_o(void)
+{
+	return 0x00000028;
+}
+static inline u32 ctxsw_prog_main_image_pm_mode_m(void)
+{
+	return 0x7 << 0;
+}
+static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
+{
+	return 0x0;
+}
+static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void)
+{
+	return 0x7 << 3;
+}
+static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void)
+{
+	return 0x8;
+}
+static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void)
+{
+	return 0x0;
+}
+static inline u32 ctxsw_prog_main_image_pm_ptr_o(void)
+{
+	return 0x0000002c;
+}
+static inline u32 ctxsw_prog_main_image_num_save_ops_o(void)
+{
+	return 0x000000f4;
+}
+static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void)
+{
+	return 0x000000f8;
+}
+static inline u32 ctxsw_prog_main_image_magic_value_o(void)
+{
+	return 0x000000fc;
+}
+static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void)
+{
+	return 0x600dc0de;
+}
+static inline u32 ctxsw_prog_local_priv_register_ctl_o(void)
+{
+	return 0x0000000c;
+}
+static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r)
+{
+	return (r >> 0) & 0xffff;
+}
+static inline u32 ctxsw_prog_local_image_ppc_info_o(void)
+{
+	return 0x000000f4;
+}
+static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r)
+{
+	return (r >> 0) & 0xffff;
+}
+static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r)
+{
+	return (r >> 16) & 0xffff;
+}
+static inline u32 ctxsw_prog_local_image_num_tpcs_o(void)
+{
+	return 0x000000f8;
+}
+static inline u32 ctxsw_prog_local_magic_value_o(void)
+{
+	return 0x000000fc;
+}
+static inline u32 ctxsw_prog_local_magic_value_v_value_v(void)
+{
+	return 0xad0becab;
+}
+static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void)
+{
+	return 0x000000ec;
+}
+static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r)
+{
+	return (r >> 0) & 0xffff;
+}
+static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r)
+{
+	return (r >> 16) & 0xff;
+}
+static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void)
+{
+	return 0x00000100;
+}
+static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void)
+{
+	return 0x00000004;
+}
+static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void)
+{
+	return 0x00000002;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void)
+{
+	return 0x000000a0;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void)
+{
+	return 2;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v)
+{
+	return (v & 0x3) << 0;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void)
+{
+	return 0x3 << 0;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r)
+{
+	return (r >> 0) & 0x3;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void)
+{
+	return 0x0;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void)
+{
+	return 0x2;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void)
+{
+	return 0x000000a4;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void)
+{
+	return 0x000000a8;
+}
+static inline u32 ctxsw_prog_main_image_misc_options_o(void)
+{
+	return 0x0000003c;
+}
+static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void)
+{
+	return 0x1 << 3;
+}
+static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void)
+{
+	return 0x0;
+}
+static inline u32 ctxsw_prog_main_image_preemption_options_o(void)
+{
+	return 0x00000060;
+}
+static inline u32 ctxsw_prog_main_image_preemption_options_control_f(u32 v)
+{
+	return (v & 0x3) << 0;
+}
+static inline u32 ctxsw_prog_main_image_preemption_options_control_cta_enabled_f(void)
+{
+	return 0x1;
+}
+#endif

drivers/gpu/nvgpu/gm206/hw_fb_gm206.h

@@ -0,0 +1,337 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_fb_gm206_h_
+#define _hw_fb_gm206_h_
+
+static inline u32 fb_fbhub_num_active_ltcs_r(void)
+{
+	return 0x00100800;
+}
+static inline u32 fb_mmu_ctrl_r(void)
+{
+	return 0x00100c80;
+}
+static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void)
+{
+	return 0x0;
+}
+static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void)
+{
+	return 0x1;
+}
+static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r)
+{
+	return (r >> 15) & 0x1;
+}
+static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void)
+{
+	return 0x0;
+}
+static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
+{
+	return (r >> 16) & 0xff;
+}
+static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r)
+{
+	return (r >> 11) & 0x1;
+}
+static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void)
+{
+	return 0x800;
+}
+static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void)
+{
+	return 0x0;
+}
+static inline u32 fb_priv_mmu_phy_secure_r(void)
+{
+	return 0x00100ce4;
+}
+static inline u32 fb_mmu_invalidate_pdb_r(void)
+{
+	return 0x00100cb8;
+}
+static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void)
+{
+	return 0x0;
+}
+static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void)
+{
+	return 0x2;
+}
+static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v)
+{
+	return (v & 0xfffffff) << 4;
+}
+static inline u32 fb_mmu_invalidate_r(void)
+{
+	return 0x00100cbc;
+}
+static inline u32 fb_mmu_invalidate_all_va_true_f(void)
+{
+	return 0x1;
+}
+static inline u32 fb_mmu_invalidate_all_pdb_true_f(void)
+{
+	return 0x2;
+}
+static inline u32 fb_mmu_invalidate_trigger_s(void)
+{
+	return 1;
+}
+static inline u32 fb_mmu_invalidate_trigger_f(u32 v)
+{
+	return (v & 0x1) << 31;
+}
+static inline u32 fb_mmu_invalidate_trigger_m(void)
+{
+	return 0x1 << 31;
+}
+static inline u32 fb_mmu_invalidate_trigger_v(u32 r)
+{
+	return (r >> 31) & 0x1;
+}
+static inline u32 fb_mmu_invalidate_trigger_true_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 fb_mmu_debug_wr_r(void)
+{
+	return 0x00100cc8;
+}
+static inline u32 fb_mmu_debug_wr_aperture_s(void)
+{
+	return 2;
+}
+static inline u32 fb_mmu_debug_wr_aperture_f(u32 v)
+{
+	return (v & 0x3) << 0;
+}
+static inline u32 fb_mmu_debug_wr_aperture_m(void)
+{
+	return 0x3 << 0;
+}
+static inline u32 fb_mmu_debug_wr_aperture_v(u32 r)
+{
+	return (r >> 0) & 0x3;
+}
+static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void)
+{
+	return 0x0;
+}
+static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void)
+{
+	return 0x2;
+}
+static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void)
+{
+	return 0x3;
+}
+static inline u32 fb_mmu_debug_wr_vol_false_f(void)
+{
+	return 0x0;
+}
+static inline u32 fb_mmu_debug_wr_vol_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fb_mmu_debug_wr_vol_true_f(void)
+{
+	return 0x4;
+}
+static inline u32 fb_mmu_debug_wr_addr_f(u32 v)
+{
+	return (v & 0xfffffff) << 4;
+}
+static inline u32 fb_mmu_debug_wr_addr_alignment_v(void)
+{
+	return 0x0000000c;
+}
+static inline u32 fb_mmu_debug_rd_r(void)
+{
+	return 0x00100ccc;
+}
+static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void)
+{
+	return 0x0;
+}
+static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void)
+{
+	return 0x2;
+}
+static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void)
+{
+	return 0x3;
+}
+static inline u32 fb_mmu_debug_rd_vol_false_f(void)
+{
+	return 0x0;
+}
+static inline u32 fb_mmu_debug_rd_addr_f(u32 v)
+{
+	return (v & 0xfffffff) << 4;
+}
+static inline u32 fb_mmu_debug_rd_addr_alignment_v(void)
+{
+	return 0x0000000c;
+}
+static inline u32 fb_mmu_debug_ctrl_r(void)
+{
+	return 0x00100cc4;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r)
+{
+	return (r >> 16) & 0x1;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_m(void)
+{
+	return 0x1 << 16;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_enabled_f(void)
+{
+	return 0x10000;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void)
+{
+	return 0x0;
+}
+static inline u32 fb_mmu_vpr_info_r(void)
+{
+	return 0x00100cd0;
+}
+static inline u32 fb_mmu_vpr_info_index_f(u32 v)
+{
+	return (v & 0x3) << 0;
+}
+static inline u32 fb_mmu_vpr_info_index_v(u32 r)
+{
+	return (r >> 0) & 0x3;
+}
+static inline u32 fb_mmu_vpr_info_index_addr_lo_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 fb_mmu_vpr_info_index_addr_hi_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fb_mmu_vpr_info_index_cya_lo_v(void)
+{
+	return 0x00000002;
+}
+static inline u32 fb_mmu_vpr_info_index_cya_hi_v(void)
+{
+	return 0x00000003;
+}
+static inline u32 fb_mmu_vpr_info_fetch_f(u32 v)
+{
+	return (v & 0x1) << 2;
+}
+static inline u32 fb_mmu_vpr_info_fetch_v(u32 r)
+{
+	return (r >> 2) & 0x1;
+}
+static inline u32 fb_mmu_vpr_info_fetch_false_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 fb_mmu_vpr_info_fetch_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fb_mmu_wpr_info_r(void)
+{
+	return 0x00100cd4;
+}
+static inline u32 fb_mmu_wpr_info_index_f(u32 v)
+{
+	return (v & 0xf) << 0;
+}
+static inline u32 fb_mmu_wpr_info_index_allow_read_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 fb_mmu_wpr_info_index_allow_write_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fb_mmu_wpr_info_index_wpr1_addr_lo_v(void)
+{
+	return 0x00000002;
+}
+static inline u32 fb_mmu_wpr_info_index_wpr1_addr_hi_v(void)
+{
+	return 0x00000003;
+}
+static inline u32 fb_mmu_wpr_info_index_wpr2_addr_lo_v(void)
+{
+	return 0x00000004;
+}
+static inline u32 fb_mmu_wpr_info_index_wpr2_addr_hi_v(void)
+{
+	return 0x00000005;
+}
+static inline u32 fb_niso_flush_sysmem_addr_r(void)
+{
+	return 0x00100c10;
+}
+#endif

drivers/gpu/nvgpu/gm206/hw_fifo_gm206.h

@@ -0,0 +1,553 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_fifo_gm206_h_
+#define _hw_fifo_gm206_h_
+
+static inline u32 fifo_bar1_base_r(void)
+{
+	return 0x00002254;
+}
+static inline u32 fifo_bar1_base_ptr_f(u32 v)
+{
+	return (v & 0xfffffff) << 0;
+}
+static inline u32 fifo_bar1_base_ptr_align_shift_v(void)
+{
+	return 0x0000000c;
+}
+static inline u32 fifo_bar1_base_valid_false_f(void)
+{
+	return 0x0;
+}
+static inline u32 fifo_bar1_base_valid_true_f(void)
+{
+	return 0x10000000;
+}
+static inline u32 fifo_runlist_base_r(void)
+{
+	return 0x00002270;
+}
+static inline u32 fifo_runlist_base_ptr_f(u32 v)
+{
+	return (v & 0xfffffff) << 0;
+}
+static inline u32 fifo_runlist_base_target_vid_mem_f(void)
+{
+	return 0x0;
+}
+static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void)
+{
+	return 0x30000000;
+}
+static inline u32 fifo_runlist_r(void)
+{
+	return 0x00002274;
+}
+static inline u32 fifo_runlist_engine_f(u32 v)
+{
+	return (v & 0xf) << 20;
+}
+static inline u32 fifo_eng_runlist_base_r(u32 i)
+{
+	return 0x00002280 + i*8;
+}
+static inline u32 fifo_eng_runlist_base__size_1_v(void)
+{
+	return 0x00000007;
+}
+static inline u32 fifo_eng_runlist_r(u32 i)
+{
+	return 0x00002284 + i*8;
+}
+static inline u32 fifo_eng_runlist__size_1_v(void)
+{
+	return 0x00000007;
+}
+static inline u32 fifo_eng_runlist_length_f(u32 v)
+{
+	return (v & 0xffff) << 0;
+}
+static inline u32 fifo_eng_runlist_length_max_v(void)
+{
+	return 0x0000ffff;
+}
+static inline u32 fifo_eng_runlist_pending_true_f(void)
+{
+	return 0x100000;
+}
+static inline u32 fifo_pb_timeslice_r(u32 i)
+{
+	return 0x00002350 + i*4;
+}
+static inline u32 fifo_pb_timeslice_timeout_16_f(void)
+{
+	return 0x10;
+}
+static inline u32 fifo_pb_timeslice_timescale_0_f(void)
+{
+	return 0x0;
+}
+static inline u32 fifo_pb_timeslice_enable_true_f(void)
+{
+	return 0x10000000;
+}
+static inline u32 fifo_pbdma_map_r(u32 i)
+{
+	return 0x00002390 + i*4;
+}
+static inline u32 fifo_intr_0_r(void)
+{
+	return 0x00002100;
+}
+static inline u32 fifo_intr_0_bind_error_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 fifo_intr_0_bind_error_reset_f(void)
+{
+	return 0x1;
+}
+static inline u32 fifo_intr_0_sched_error_pending_f(void)
+{
+	return 0x100;
+}
+static inline u32 fifo_intr_0_sched_error_reset_f(void)
+{
+	return 0x100;
+}
+static inline u32 fifo_intr_0_chsw_error_pending_f(void)
+{
+	return 0x10000;
+}
+static inline u32 fifo_intr_0_chsw_error_reset_f(void)
+{
+	return 0x10000;
+}
+static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void)
+{
+	return 0x800000;
+}
+static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void)
+{
+	return 0x800000;
+}
+static inline u32 fifo_intr_0_lb_error_pending_f(void)
+{
+	return 0x1000000;
+}
+static inline u32 fifo_intr_0_lb_error_reset_f(void)
+{
+	return 0x1000000;
+}
+static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void)
+{
+	return 0x8000000;
+}
+static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void)
+{
+	return 0x8000000;
+}
+static inline u32 fifo_intr_0_mmu_fault_pending_f(void)
+{
+	return 0x10000000;
+}
+static inline u32 fifo_intr_0_pbdma_intr_pending_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 fifo_intr_0_runlist_event_pending_f(void)
+{
+	return 0x40000000;
+}
+static inline u32 fifo_intr_0_channel_intr_pending_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 fifo_intr_en_0_r(void)
+{
+	return 0x00002140;
+}
+static inline u32 fifo_intr_en_0_sched_error_f(u32 v)
+{
+	return (v & 0x1) << 8;
+}
+static inline u32 fifo_intr_en_0_sched_error_m(void)
+{
+	return 0x1 << 8;
+}
+static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v)
+{
+	return (v & 0x1) << 28;
+}
+static inline u32 fifo_intr_en_0_mmu_fault_m(void)
+{
+	return 0x1 << 28;
+}
+static inline u32 fifo_intr_en_1_r(void)
+{
+	return 0x00002528;
+}
+static inline u32 fifo_intr_bind_error_r(void)
+{
+	return 0x0000252c;
+}
+static inline u32 fifo_intr_sched_error_r(void)
+{
+	return 0x0000254c;
+}
+static inline u32 fifo_intr_sched_error_code_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void)
+{
+	return 0x0000000a;
+}
+static inline u32 fifo_intr_chsw_error_r(void)
+{
+	return 0x0000256c;
+}
+static inline u32 fifo_intr_mmu_fault_id_r(void)
+{
+	return 0x0000259c;
+}
+static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void)
+{
+	return 0x0;
+}
+static inline u32 fifo_intr_mmu_fault_inst_r(u32 i)
+{
+	return 0x00002800 + i*16;
+}
+static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r)
+{
+	return (r >> 0) & 0xfffffff;
+}
+static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void)
+{
+	return 0x0000000c;
+}
+static inline u32 fifo_intr_mmu_fault_lo_r(u32 i)
+{
+	return 0x00002804 + i*16;
+}
+static inline u32 fifo_intr_mmu_fault_hi_r(u32 i)
+{
+	return 0x00002808 + i*16;
+}
+static inline u32 fifo_intr_mmu_fault_info_r(u32 i)
+{
+	return 0x0000280c + i*16;
+}
+static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r)
+{
+	return (r >> 0) & 0xf;
+}
+static inline u32 fifo_intr_mmu_fault_info_engine_subid_v(u32 r)
+{
+	return (r >> 6) & 0x1;
+}
+static inline u32 fifo_intr_mmu_fault_info_engine_subid_gpc_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 fifo_intr_mmu_fault_info_engine_subid_hub_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r)
+{
+	return (r >> 8) & 0x3f;
+}
+static inline u32 fifo_intr_pbdma_id_r(void)
+{
+	return 0x000025a0;
+}
+static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i)
+{
+	return (v & 0x1) << (0 + i*1);
+}
+static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
+{
+	return 0x00000003;
+}
+static inline u32 fifo_intr_runlist_r(void)
+{
+	return 0x00002a00;
+}
+static inline u32 fifo_fb_timeout_r(void)
+{
+	return 0x00002a04;
+}
+static inline u32 fifo_fb_timeout_period_m(void)
+{
+	return 0x3fffffff << 0;
+}
+static inline u32 fifo_fb_timeout_period_max_f(void)
+{
+	return 0x3fffffff;
+}
+static inline u32 fifo_error_sched_disable_r(void)
+{
+	return 0x0000262c;
+}
+static inline u32 fifo_sched_disable_r(void)
+{
+	return 0x00002630;
+}
+static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i)
+{
+	return (v & 0x1) << (0 + i*1);
+}
+static inline u32 fifo_sched_disable_runlist_m(u32 i)
+{
+	return 0x1 << (0 + i*1);
+}
+static inline u32 fifo_sched_disable_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fifo_preempt_r(void)
+{
+	return 0x00002634;
+}
+static inline u32 fifo_preempt_pending_true_f(void)
+{
+	return 0x100000;
+}
+static inline u32 fifo_preempt_type_channel_f(void)
+{
+	return 0x0;
+}
+static inline u32 fifo_preempt_type_tsg_f(void)
+{
+	return 0x1000000;
+}
+static inline u32 fifo_preempt_chid_f(u32 v)
+{
+	return (v & 0xfff) << 0;
+}
+static inline u32 fifo_preempt_id_f(u32 v)
+{
+	return (v & 0xfff) << 0;
+}
+static inline u32 fifo_trigger_mmu_fault_r(u32 i)
+{
+	return 0x00002a30 + i*4;
+}
+static inline u32 fifo_trigger_mmu_fault_id_f(u32 v)
+{
+	return (v & 0x1f) << 0;
+}
+static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v)
+{
+	return (v & 0x1) << 8;
+}
+static inline u32 fifo_engine_status_r(u32 i)
+{
+	return 0x00002640 + i*8;
+}
+static inline u32 fifo_engine_status__size_1_v(void)
+{
+	return 0x00000008;
+}
+static inline u32 fifo_engine_status_id_v(u32 r)
+{
+	return (r >> 0) & 0xfff;
+}
+static inline u32 fifo_engine_status_id_type_v(u32 r)
+{
+	return (r >> 12) & 0x1;
+}
+static inline u32 fifo_engine_status_id_type_chid_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 fifo_engine_status_id_type_tsgid_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fifo_engine_status_ctx_status_v(u32 r)
+{
+	return (r >> 13) & 0x7;
+}
+static inline u32 fifo_engine_status_ctx_status_valid_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void)
+{
+	return 0x00000005;
+}
+static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void)
+{
+	return 0x00000006;
+}
+static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void)
+{
+	return 0x00000007;
+}
+static inline u32 fifo_engine_status_next_id_v(u32 r)
+{
+	return (r >> 16) & 0xfff;
+}
+static inline u32 fifo_engine_status_next_id_type_v(u32 r)
+{
+	return (r >> 28) & 0x1;
+}
+static inline u32 fifo_engine_status_next_id_type_chid_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 fifo_engine_status_faulted_v(u32 r)
+{
+	return (r >> 30) & 0x1;
+}
+static inline u32 fifo_engine_status_faulted_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fifo_engine_status_engine_v(u32 r)
+{
+	return (r >> 31) & 0x1;
+}
+static inline u32 fifo_engine_status_engine_idle_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 fifo_engine_status_engine_busy_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fifo_engine_status_ctxsw_v(u32 r)
+{
+	return (r >> 15) & 0x1;
+}
+static inline u32 fifo_engine_status_ctxsw_in_progress_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fifo_engine_status_ctxsw_in_progress_f(void)
+{
+	return 0x8000;
+}
+static inline u32 fifo_pbdma_status_r(u32 i)
+{
+	return 0x00003080 + i*4;
+}
+static inline u32 fifo_pbdma_status__size_1_v(void)
+{
+	return 0x00000003;
+}
+static inline u32 fifo_pbdma_status_id_v(u32 r)
+{
+	return (r >> 0) & 0xfff;
+}
+static inline u32 fifo_pbdma_status_id_type_v(u32 r)
+{
+	return (r >> 12) & 0x1;
+}
+static inline u32 fifo_pbdma_status_id_type_chid_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 fifo_pbdma_status_id_type_tsgid_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fifo_pbdma_status_chan_status_v(u32 r)
+{
+	return (r >> 13) & 0x7;
+}
+static inline u32 fifo_pbdma_status_chan_status_valid_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void)
+{
+	return 0x00000005;
+}
+static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void)
+{
+	return 0x00000006;
+}
+static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void)
+{
+	return 0x00000007;
+}
+static inline u32 fifo_pbdma_status_next_id_v(u32 r)
+{
+	return (r >> 16) & 0xfff;
+}
+static inline u32 fifo_pbdma_status_next_id_type_v(u32 r)
+{
+	return (r >> 28) & 0x1;
+}
+static inline u32 fifo_pbdma_status_next_id_type_chid_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 fifo_pbdma_status_chsw_v(u32 r)
+{
+	return (r >> 15) & 0x1;
+}
+static inline u32 fifo_pbdma_status_chsw_in_progress_v(void)
+{
+	return 0x00000001;
+}
+#endif

drivers/gpu/nvgpu/gm206/hw_flush_gm206.h

@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_flush_gm206_h_
+#define _hw_flush_gm206_h_
+
+static inline u32 flush_l2_system_invalidate_r(void)
+{
+	return 0x00070004;
+}
+static inline u32 flush_l2_system_invalidate_pending_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 flush_l2_system_invalidate_pending_busy_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 flush_l2_system_invalidate_pending_busy_f(void)
+{
+	return 0x1;
+}
+static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r)
+{
+	return (r >> 1) & 0x1;
+}
+static inline u32 flush_l2_system_invalidate_outstanding_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 flush_l2_flush_dirty_r(void)
+{
+	return 0x00070010;
+}
+static inline u32 flush_l2_flush_dirty_pending_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 flush_l2_flush_dirty_pending_empty_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 flush_l2_flush_dirty_pending_empty_f(void)
+{
+	return 0x0;
+}
+static inline u32 flush_l2_flush_dirty_pending_busy_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 flush_l2_flush_dirty_pending_busy_f(void)
+{
+	return 0x1;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r)
+{
+	return (r >> 1) & 0x1;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_false_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_false_f(void)
+{
+	return 0x0;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 flush_l2_clean_comptags_r(void)
+{
+	return 0x0007000c;
+}
+static inline u32 flush_l2_clean_comptags_pending_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 flush_l2_clean_comptags_pending_empty_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 flush_l2_clean_comptags_pending_empty_f(void)
+{
+	return 0x0;
+}
+static inline u32 flush_l2_clean_comptags_pending_busy_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 flush_l2_clean_comptags_pending_busy_f(void)
+{
+	return 0x1;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r)
+{
+	return (r >> 1) & 0x1;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_false_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_false_f(void)
+{
+	return 0x0;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 flush_fb_flush_r(void)
+{
+	return 0x00070000;
+}
+static inline u32 flush_fb_flush_pending_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 flush_fb_flush_pending_busy_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 flush_fb_flush_pending_busy_f(void)
+{
+	return 0x1;
+}
+static inline u32 flush_fb_flush_outstanding_v(u32 r)
+{
+	return (r >> 1) & 0x1;
+}
+static inline u32 flush_fb_flush_outstanding_true_v(void)
+{
+	return 0x00000001;
+}
+#endif

drivers/gpu/nvgpu/gm206/hw_fuse_gm206.h

@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_fuse_gm206_h_
+#define _hw_fuse_gm206_h_
+
+static inline u32 fuse_status_opt_tpc_gpc_r(u32 i)
+{
+	return 0x00021c38 + i*4;
+}
+static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i)
+{
+	return 0x00021838 + i*4;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void)
+{
+	return 0x00021944;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v)
+{
+	return (v & 0x3) << 0;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void)
+{
+	return 0x3 << 0;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r)
+{
+	return (r >> 0) & 0x3;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void)
+{
+	return 0x00021948;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void)
+{
+	return 0x1 << 0;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void)
+{
+	return 0x1;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void)
+{
+	return 0x0;
+}
+static inline u32 fuse_status_opt_fbio_r(void)
+{
+	return 0x00021c14;
+}
+static inline u32 fuse_status_opt_fbio_data_f(u32 v)
+{
+	return (v & 0xffff) << 0;
+}
+static inline u32 fuse_status_opt_fbio_data_m(void)
+{
+	return 0xffff << 0;
+}
+static inline u32 fuse_status_opt_fbio_data_v(u32 r)
+{
+	return (r >> 0) & 0xffff;
+}
+static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i)
+{
+	return 0x00021d70 + i*4;
+}
+static inline u32 fuse_status_opt_fbp_r(void)
+{
+	return 0x00021d38;
+}
+static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i)
+{
+	return (r >> (0 + i*0)) & 0x1;
+}
+#endif

drivers/gpu/nvgpu/gm206/hw_ltc_gm206.h

@@ -0,0 +1,497 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ltc_gm206_h_
+#define _hw_ltc_gm206_h_
+
+static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void)
+{
+	return 0x0014046c;
+}
+static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void)
+{
+	return 0x00140518;
+}
+static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void)
+{
+	return 0x0017e318;
+}
+static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void)
+{
+	return 0x1 << 15;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void)
+{
+	return 0x00140494;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r)
+{
+	return (r >> 0) & 0xffff;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r)
+{
+	return (r >> 16) & 0x3;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void)
+{
+	return 0x00000002;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void)
+{
+	return 0x0017e26c;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void)
+{
+	return 0x1;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void)
+{
+	return 0x2;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r)
+{
+	return (r >> 2) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void)
+{
+	return 0x4;
+}
+static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void)
+{
+	return 0x0014046c;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void)
+{
+	return 0x0017e270;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v)
+{
+	return (v & 0x1ffff) << 0;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void)
+{
+	return 0x0017e274;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v)
+{
+	return (v & 0x1ffff) << 0;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void)
+{
+	return 0x0001ffff;
+}
+static inline u32 ltc_ltcs_ltss_cbc_base_r(void)
+{
+	return 0x0017e278;
+}
+static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void)
+{
+	return 0x0000000b;
+}
+static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r)
+{
+	return (r >> 0) & 0x3ffffff;
+}
+static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void)
+{
+	return 0x0017e27c;
+}
+static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void)
+{
+	return 0x0017e000;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_r(void)
+{
+	return 0x0017e280;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r)
+{
+	return (r >> 0) & 0xffff;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r)
+{
+	return (r >> 24) & 0xf;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r)
+{
+	return (r >> 28) & 0xf;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void)
+{
+	return 0x0017e2ac;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v)
+{
+	return (v & 0x1f) << 16;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void)
+{
+	return 0x0017e338;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v)
+{
+	return (v & 0xf) << 0;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i)
+{
+	return 0x0017e33c + i*4;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void)
+{
+	return 0x00000004;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void)
+{
+	return 0x0017e34c;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void)
+{
+	return 32;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void)
+{
+	return 0xffffffff << 0;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r)
+{
+	return (r >> 0) & 0xffffffff;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void)
+{
+	return 0x0017e2b0;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void)
+{
+	return 0x10000000;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_r(void)
+{
+	return 0x0017e214;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_r(void)
+{
+	return 0x00140214;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 ltc_ltc1_ltss_g_elpg_r(void)
+{
+	return 0x00142214;
+}
+static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 ltc_ltcs_ltss_intr_r(void)
+{
+	return 0x0017e20c;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void)
+{
+	return 0x1 << 20;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void)
+{
+	return 0x1 << 30;
+}
+static inline u32 ltc_ltc0_lts0_intr_r(void)
+{
+	return 0x0014040c;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void)
+{
+	return 0x0017e2a0;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r)
+{
+	return (r >> 8) & 0xf;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void)
+{
+	return 0x00000003;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void)
+{
+	return 0x300;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r)
+{
+	return (r >> 28) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void)
+{
+	return 0x10000000;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r)
+{
+	return (r >> 29) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r)
+{
+	return (r >> 30) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void)
+{
+	return 0x40000000;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void)
+{
+	return 0x0017e2a4;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r)
+{
+	return (r >> 8) & 0xf;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void)
+{
+	return 0x00000003;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void)
+{
+	return 0x300;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r)
+{
+	return (r >> 16) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void)
+{
+	return 0x10000;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r)
+{
+	return (r >> 28) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void)
+{
+	return 0x10000000;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r)
+{
+	return (r >> 29) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r)
+{
+	return (r >> 30) & 0x1;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void)
+{
+	return 0x40000000;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void)
+{
+	return 0x001402a0;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void)
+{
+	return 0x001402a4;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void)
+{
+	return 0x001422a0;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void)
+{
+	return 0x001422a4;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void)
+{
+	return 0x1;
+}
+#endif

drivers/gpu/nvgpu/gm206/hw_mc_gm206.h

@@ -0,0 +1,281 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_mc_gm206_h_
+#define _hw_mc_gm206_h_
+
+static inline u32 mc_boot_0_r(void)
+{
+	return 0x00000000;
+}
+static inline u32 mc_boot_0_architecture_v(u32 r)
+{
+	return (r >> 24) & 0x1f;
+}
+static inline u32 mc_boot_0_implementation_v(u32 r)
+{
+	return (r >> 20) & 0xf;
+}
+static inline u32 mc_boot_0_major_revision_v(u32 r)
+{
+	return (r >> 4) & 0xf;
+}
+static inline u32 mc_boot_0_minor_revision_v(u32 r)
+{
+	return (r >> 0) & 0xf;
+}
+static inline u32 mc_intr_r(u32 i)
+{
+	return 0x00000100 + i*4;
+}
+static inline u32 mc_intr_pfifo_pending_f(void)
+{
+	return 0x100;
+}
+static inline u32 mc_intr_pmu_pending_f(void)
+{
+	return 0x1000000;
+}
+static inline u32 mc_intr_ltc_pending_f(void)
+{
+	return 0x2000000;
+}
+static inline u32 mc_intr_priv_ring_pending_f(void)
+{
+	return 0x40000000;
+}
+static inline u32 mc_intr_pbus_pending_f(void)
+{
+	return 0x10000000;
+}
+static inline u32 mc_intr_mask_0_r(void)
+{
+	return 0x00000640;
+}
+static inline u32 mc_intr_mask_0_pmu_enabled_f(void)
+{
+	return 0x1000000;
+}
+static inline u32 mc_intr_en_0_r(void)
+{
+	return 0x00000140;
+}
+static inline u32 mc_intr_en_0_inta_disabled_f(void)
+{
+	return 0x0;
+}
+static inline u32 mc_intr_en_0_inta_hardware_f(void)
+{
+	return 0x1;
+}
+static inline u32 mc_intr_mask_1_r(void)
+{
+	return 0x00000644;
+}
+static inline u32 mc_intr_mask_1_pmu_s(void)
+{
+	return 1;
+}
+static inline u32 mc_intr_mask_1_pmu_f(u32 v)
+{
+	return (v & 0x1) << 24;
+}
+static inline u32 mc_intr_mask_1_pmu_m(void)
+{
+	return 0x1 << 24;
+}
+static inline u32 mc_intr_mask_1_pmu_v(u32 r)
+{
+	return (r >> 24) & 0x1;
+}
+static inline u32 mc_intr_mask_1_pmu_enabled_f(void)
+{
+	return 0x1000000;
+}
+static inline u32 mc_intr_en_1_r(void)
+{
+	return 0x00000144;
+}
+static inline u32 mc_intr_en_1_inta_disabled_f(void)
+{
+	return 0x0;
+}
+static inline u32 mc_intr_en_1_inta_hardware_f(void)
+{
+	return 0x1;
+}
+static inline u32 mc_enable_r(void)
+{
+	return 0x00000200;
+}
+static inline u32 mc_enable_xbar_enabled_f(void)
+{
+	return 0x4;
+}
+static inline u32 mc_enable_l2_enabled_f(void)
+{
+	return 0x8;
+}
+static inline u32 mc_enable_pmedia_s(void)
+{
+	return 1;
+}
+static inline u32 mc_enable_pmedia_f(u32 v)
+{
+	return (v & 0x1) << 4;
+}
+static inline u32 mc_enable_pmedia_m(void)
+{
+	return 0x1 << 4;
+}
+static inline u32 mc_enable_pmedia_v(u32 r)
+{
+	return (r >> 4) & 0x1;
+}
+static inline u32 mc_enable_priv_ring_enabled_f(void)
+{
+	return 0x20;
+}
+static inline u32 mc_enable_ce0_m(void)
+{
+	return 0x1 << 6;
+}
+static inline u32 mc_enable_pfifo_enabled_f(void)
+{
+	return 0x100;
+}
+static inline u32 mc_enable_pgraph_enabled_f(void)
+{
+	return 0x1000;
+}
+static inline u32 mc_enable_pwr_v(u32 r)
+{
+	return (r >> 13) & 0x1;
+}
+static inline u32 mc_enable_pwr_disabled_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 mc_enable_pwr_enabled_f(void)
+{
+	return 0x2000;
+}
+static inline u32 mc_enable_pfb_enabled_f(void)
+{
+	return 0x100000;
+}
+static inline u32 mc_enable_ce2_m(void)
+{
+	return 0x1 << 21;
+}
+static inline u32 mc_enable_ce2_enabled_f(void)
+{
+	return 0x200000;
+}
+static inline u32 mc_enable_blg_enabled_f(void)
+{
+	return 0x8000000;
+}
+static inline u32 mc_enable_perfmon_enabled_f(void)
+{
+	return 0x10000000;
+}
+static inline u32 mc_enable_hub_enabled_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 mc_intr_ltc_r(void)
+{
+	return 0x0000017c;
+}
+static inline u32 mc_enable_pb_r(void)
+{
+	return 0x00000204;
+}
+static inline u32 mc_enable_pb_0_s(void)
+{
+	return 1;
+}
+static inline u32 mc_enable_pb_0_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 mc_enable_pb_0_m(void)
+{
+	return 0x1 << 0;
+}
+static inline u32 mc_enable_pb_0_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 mc_enable_pb_0_enabled_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 mc_enable_pb_sel_f(u32 v, u32 i)
+{
+	return (v & 0x1) << (0 + i*1);
+}
+static inline u32 mc_elpg_enable_r(void)
+{
+	return 0x0000020c;
+}
+static inline u32 mc_elpg_enable_xbar_enabled_f(void)
+{
+	return 0x4;
+}
+static inline u32 mc_elpg_enable_pfb_enabled_f(void)
+{
+	return 0x100000;
+}
+static inline u32 mc_elpg_enable_hub_enabled_f(void)
+{
+	return 0x20000000;
+}
+#endif

drivers/gpu/nvgpu/gm206/hw_pbdma_gm206.h

@@ -0,0 +1,505 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pbdma_gm206_h_
+#define _hw_pbdma_gm206_h_
+
+static inline u32 pbdma_gp_entry1_r(void)
+{
+	return 0x10000004;
+}
+static inline u32 pbdma_gp_entry1_get_hi_v(u32 r)
+{
+	return (r >> 0) & 0xff;
+}
+static inline u32 pbdma_gp_entry1_length_f(u32 v)
+{
+	return (v & 0x1fffff) << 10;
+}
+static inline u32 pbdma_gp_entry1_length_v(u32 r)
+{
+	return (r >> 10) & 0x1fffff;
+}
+static inline u32 pbdma_gp_base_r(u32 i)
+{
+	return 0x00040048 + i*8192;
+}
+static inline u32 pbdma_gp_base__size_1_v(void)
+{
+	return 0x00000003;
+}
+static inline u32 pbdma_gp_base_offset_f(u32 v)
+{
+	return (v & 0x1fffffff) << 3;
+}
+static inline u32 pbdma_gp_base_rsvd_s(void)
+{
+	return 3;
+}
+static inline u32 pbdma_gp_base_hi_r(u32 i)
+{
+	return 0x0004004c + i*8192;
+}
+static inline u32 pbdma_gp_base_hi_offset_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 pbdma_gp_base_hi_limit2_f(u32 v)
+{
+	return (v & 0x1f) << 16;
+}
+static inline u32 pbdma_gp_fetch_r(u32 i)
+{
+	return 0x00040050 + i*8192;
+}
+static inline u32 pbdma_gp_get_r(u32 i)
+{
+	return 0x00040014 + i*8192;
+}
+static inline u32 pbdma_gp_put_r(u32 i)
+{
+	return 0x00040000 + i*8192;
+}
+static inline u32 pbdma_pb_fetch_r(u32 i)
+{
+	return 0x00040054 + i*8192;
+}
+static inline u32 pbdma_pb_fetch_hi_r(u32 i)
+{
+	return 0x00040058 + i*8192;
+}
+static inline u32 pbdma_get_r(u32 i)
+{
+	return 0x00040018 + i*8192;
+}
+static inline u32 pbdma_get_hi_r(u32 i)
+{
+	return 0x0004001c + i*8192;
+}
+static inline u32 pbdma_put_r(u32 i)
+{
+	return 0x0004005c + i*8192;
+}
+static inline u32 pbdma_put_hi_r(u32 i)
+{
+	return 0x00040060 + i*8192;
+}
+static inline u32 pbdma_formats_r(u32 i)
+{
+	return 0x0004009c + i*8192;
+}
+static inline u32 pbdma_formats_gp_fermi0_f(void)
+{
+	return 0x0;
+}
+static inline u32 pbdma_formats_pb_fermi1_f(void)
+{
+	return 0x100;
+}
+static inline u32 pbdma_formats_mp_fermi0_f(void)
+{
+	return 0x0;
+}
+static inline u32 pbdma_pb_header_r(u32 i)
+{
+	return 0x00040084 + i*8192;
+}
+static inline u32 pbdma_pb_header_priv_user_f(void)
+{
+	return 0x0;
+}
+static inline u32 pbdma_pb_header_method_zero_f(void)
+{
+	return 0x0;
+}
+static inline u32 pbdma_pb_header_subchannel_zero_f(void)
+{
+	return 0x0;
+}
+static inline u32 pbdma_pb_header_level_main_f(void)
+{
+	return 0x0;
+}
+static inline u32 pbdma_pb_header_first_true_f(void)
+{
+	return 0x400000;
+}
+static inline u32 pbdma_pb_header_type_inc_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 pbdma_pb_header_type_non_inc_f(void)
+{
+	return 0x60000000;
+}
+static inline u32 pbdma_hdr_shadow_r(u32 i)
+{
+	return 0x00040118 + i*8192;
+}
+static inline u32 pbdma_subdevice_r(u32 i)
+{
+	return 0x00040094 + i*8192;
+}
+static inline u32 pbdma_subdevice_id_f(u32 v)
+{
+	return (v & 0xfff) << 0;
+}
+static inline u32 pbdma_subdevice_status_active_f(void)
+{
+	return 0x10000000;
+}
+static inline u32 pbdma_subdevice_channel_dma_enable_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 pbdma_method0_r(u32 i)
+{
+	return 0x000400c0 + i*8192;
+}
+static inline u32 pbdma_method0_fifo_size_v(void)
+{
+	return 0x00000004;
+}
+static inline u32 pbdma_method0_addr_f(u32 v)
+{
+	return (v & 0xfff) << 2;
+}
+static inline u32 pbdma_method0_addr_v(u32 r)
+{
+	return (r >> 2) & 0xfff;
+}
+static inline u32 pbdma_method0_subch_v(u32 r)
+{
+	return (r >> 16) & 0x7;
+}
+static inline u32 pbdma_method0_first_true_f(void)
+{
+	return 0x400000;
+}
+static inline u32 pbdma_method0_valid_true_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 pbdma_method1_r(u32 i)
+{
+	return 0x000400c8 + i*8192;
+}
+static inline u32 pbdma_method2_r(u32 i)
+{
+	return 0x000400d0 + i*8192;
+}
+static inline u32 pbdma_method3_r(u32 i)
+{
+	return 0x000400d8 + i*8192;
+}
+static inline u32 pbdma_data0_r(u32 i)
+{
+	return 0x000400c4 + i*8192;
+}
+static inline u32 pbdma_target_r(u32 i)
+{
+	return 0x000400ac + i*8192;
+}
+static inline u32 pbdma_target_engine_sw_f(void)
+{
+	return 0x1f;
+}
+static inline u32 pbdma_acquire_r(u32 i)
+{
+	return 0x00040030 + i*8192;
+}
+static inline u32 pbdma_acquire_retry_man_2_f(void)
+{
+	return 0x2;
+}
+static inline u32 pbdma_acquire_retry_exp_2_f(void)
+{
+	return 0x100;
+}
+static inline u32 pbdma_acquire_timeout_exp_max_f(void)
+{
+	return 0x7800;
+}
+static inline u32 pbdma_acquire_timeout_man_max_f(void)
+{
+	return 0x7fff8000;
+}
+static inline u32 pbdma_acquire_timeout_en_disable_f(void)
+{
+	return 0x0;
+}
+static inline u32 pbdma_status_r(u32 i)
+{
+	return 0x00040100 + i*8192;
+}
+static inline u32 pbdma_channel_r(u32 i)
+{
+	return 0x00040120 + i*8192;
+}
+static inline u32 pbdma_signature_r(u32 i)
+{
+	return 0x00040010 + i*8192;
+}
+static inline u32 pbdma_signature_hw_valid_f(void)
+{
+	return 0xface;
+}
+static inline u32 pbdma_signature_sw_zero_f(void)
+{
+	return 0x0;
+}
+static inline u32 pbdma_userd_r(u32 i)
+{
+	return 0x00040008 + i*8192;
+}
+static inline u32 pbdma_userd_target_vid_mem_f(void)
+{
+	return 0x0;
+}
+static inline u32 pbdma_userd_target_sys_mem_coh_f(void)
+{
+	return 0x2;
+}
+static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void)
+{
+	return 0x3;
+}
+static inline u32 pbdma_userd_addr_f(u32 v)
+{
+	return (v & 0x7fffff) << 9;
+}
+static inline u32 pbdma_userd_hi_r(u32 i)
+{
+	return 0x0004000c + i*8192;
+}
+static inline u32 pbdma_userd_hi_addr_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 pbdma_hce_ctrl_r(u32 i)
+{
+	return 0x000400e4 + i*8192;
+}
+static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void)
+{
+	return 0x20;
+}
+static inline u32 pbdma_intr_0_r(u32 i)
+{
+	return 0x00040108 + i*8192;
+}
+static inline u32 pbdma_intr_0_memreq_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 pbdma_intr_0_memreq_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 pbdma_intr_0_memack_timeout_pending_f(void)
+{
+	return 0x2;
+}
+static inline u32 pbdma_intr_0_memack_extra_pending_f(void)
+{
+	return 0x4;
+}
+static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void)
+{
+	return 0x8;
+}
+static inline u32 pbdma_intr_0_memdat_extra_pending_f(void)
+{
+	return 0x10;
+}
+static inline u32 pbdma_intr_0_memflush_pending_f(void)
+{
+	return 0x20;
+}
+static inline u32 pbdma_intr_0_memop_pending_f(void)
+{
+	return 0x40;
+}
+static inline u32 pbdma_intr_0_lbconnect_pending_f(void)
+{
+	return 0x80;
+}
+static inline u32 pbdma_intr_0_lbreq_pending_f(void)
+{
+	return 0x100;
+}
+static inline u32 pbdma_intr_0_lback_timeout_pending_f(void)
+{
+	return 0x200;
+}
+static inline u32 pbdma_intr_0_lback_extra_pending_f(void)
+{
+	return 0x400;
+}
+static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void)
+{
+	return 0x800;
+}
+static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void)
+{
+	return 0x1000;
+}
+static inline u32 pbdma_intr_0_gpfifo_pending_f(void)
+{
+	return 0x2000;
+}
+static inline u32 pbdma_intr_0_gpptr_pending_f(void)
+{
+	return 0x4000;
+}
+static inline u32 pbdma_intr_0_gpentry_pending_f(void)
+{
+	return 0x8000;
+}
+static inline u32 pbdma_intr_0_gpcrc_pending_f(void)
+{
+	return 0x10000;
+}
+static inline u32 pbdma_intr_0_pbptr_pending_f(void)
+{
+	return 0x20000;
+}
+static inline u32 pbdma_intr_0_pbentry_pending_f(void)
+{
+	return 0x40000;
+}
+static inline u32 pbdma_intr_0_pbcrc_pending_f(void)
+{
+	return 0x80000;
+}
+static inline u32 pbdma_intr_0_xbarconnect_pending_f(void)
+{
+	return 0x100000;
+}
+static inline u32 pbdma_intr_0_method_pending_f(void)
+{
+	return 0x200000;
+}
+static inline u32 pbdma_intr_0_methodcrc_pending_f(void)
+{
+	return 0x400000;
+}
+static inline u32 pbdma_intr_0_device_pending_f(void)
+{
+	return 0x800000;
+}
+static inline u32 pbdma_intr_0_semaphore_pending_f(void)
+{
+	return 0x2000000;
+}
+static inline u32 pbdma_intr_0_acquire_pending_f(void)
+{
+	return 0x4000000;
+}
+static inline u32 pbdma_intr_0_pri_pending_f(void)
+{
+	return 0x8000000;
+}
+static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 pbdma_intr_0_pbseg_pending_f(void)
+{
+	return 0x40000000;
+}
+static inline u32 pbdma_intr_0_signature_pending_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 pbdma_intr_1_r(u32 i)
+{
+	return 0x00040148 + i*8192;
+}
+static inline u32 pbdma_intr_en_0_r(u32 i)
+{
+	return 0x0004010c + i*8192;
+}
+static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void)
+{
+	return 0x100;
+}
+static inline u32 pbdma_intr_en_1_r(u32 i)
+{
+	return 0x0004014c + i*8192;
+}
+static inline u32 pbdma_intr_stall_r(u32 i)
+{
+	return 0x0004013c + i*8192;
+}
+static inline u32 pbdma_intr_stall_lbreq_enabled_f(void)
+{
+	return 0x100;
+}
+static inline u32 pbdma_udma_nop_r(void)
+{
+	return 0x00000008;
+}
+static inline u32 pbdma_runlist_timeslice_r(u32 i)
+{
+	return 0x000400f8 + i*8192;
+}
+static inline u32 pbdma_runlist_timeslice_timeout_128_f(void)
+{
+	return 0x80;
+}
+static inline u32 pbdma_runlist_timeslice_timescale_3_f(void)
+{
+	return 0x3000;
+}
+static inline u32 pbdma_runlist_timeslice_enable_true_f(void)
+{
+	return 0x10000000;
+}
+#endif

drivers/gpu/nvgpu/gm206/hw_perf_gm206.h

@@ -0,0 +1,205 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_perf_gm206_h_
+#define _hw_perf_gm206_h_
+
+static inline u32 perf_pmasys_control_r(void)
+{
+	return 0x001b4000;
+}
+static inline u32 perf_pmasys_control_membuf_status_v(u32 r)
+{
+	return (r >> 4) & 0x1;
+}
+static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void)
+{
+	return 0x10;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v)
+{
+	return (v & 0x1) << 5;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r)
+{
+	return (r >> 5) & 0x1;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void)
+{
+	return 0x20;
+}
+static inline u32 perf_pmasys_mem_block_r(void)
+{
+	return 0x001b4070;
+}
+static inline u32 perf_pmasys_mem_block_base_f(u32 v)
+{
+	return (v & 0xfffffff) << 0;
+}
+static inline u32 perf_pmasys_mem_block_target_f(u32 v)
+{
+	return (v & 0x3) << 28;
+}
+static inline u32 perf_pmasys_mem_block_target_v(u32 r)
+{
+	return (r >> 28) & 0x3;
+}
+static inline u32 perf_pmasys_mem_block_target_lfb_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 perf_pmasys_mem_block_target_lfb_f(void)
+{
+	return 0x0;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void)
+{
+	return 0x00000002;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void)
+{
+	return 0x00000003;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void)
+{
+	return 0x30000000;
+}
+static inline u32 perf_pmasys_mem_block_valid_f(u32 v)
+{
+	return (v & 0x1) << 31;
+}
+static inline u32 perf_pmasys_mem_block_valid_v(u32 r)
+{
+	return (r >> 31) & 0x1;
+}
+static inline u32 perf_pmasys_mem_block_valid_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 perf_pmasys_mem_block_valid_true_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 perf_pmasys_mem_block_valid_false_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 perf_pmasys_mem_block_valid_false_f(void)
+{
+	return 0x0;
+}
+static inline u32 perf_pmasys_outbase_r(void)
+{
+	return 0x001b4074;
+}
+static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
+{
+	return (v & 0x7ffffff) << 5;
+}
+static inline u32 perf_pmasys_outbaseupper_r(void)
+{
+	return 0x001b4078;
+}
+static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 perf_pmasys_outsize_r(void)
+{
+	return 0x001b407c;
+}
+static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
+{
+	return (v & 0x7ffffff) << 5;
+}
+static inline u32 perf_pmasys_mem_bytes_r(void)
+{
+	return 0x001b4084;
+}
+static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
+{
+	return (v & 0xfffffff) << 4;
+}
+static inline u32 perf_pmasys_mem_bump_r(void)
+{
+	return 0x001b4088;
+}
+static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
+{
+	return (v & 0xfffffff) << 4;
+}
+static inline u32 perf_pmasys_enginestatus_r(void)
+{
+	return 0x001b40a4;
+}
+static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v)
+{
+	return (v & 0x1) << 4;
+}
+static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void)
+{
+	return 0x10;
+}
+#endif

drivers/gpu/nvgpu/gm206/hw_pri_ringmaster_gm206.h

@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pri_ringmaster_gm206_h_
+#define _hw_pri_ringmaster_gm206_h_
+
+static inline u32 pri_ringmaster_command_r(void)
+{
+	return 0x0012004c;
+}
+static inline u32 pri_ringmaster_command_cmd_m(void)
+{
+	return 0x3f << 0;
+}
+static inline u32 pri_ringmaster_command_cmd_v(u32 r)
+{
+	return (r >> 0) & 0x3f;
+}
+static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 pri_ringmaster_command_cmd_start_ring_f(void)
+{
+	return 0x1;
+}
+static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void)
+{
+	return 0x2;
+}
+static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void)
+{
+	return 0x3;
+}
+static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void)
+{
+	return 0x0;
+}
+static inline u32 pri_ringmaster_command_data_r(void)
+{
+	return 0x00120048;
+}
+static inline u32 pri_ringmaster_start_results_r(void)
+{
+	return 0x00120050;
+}
+static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 pri_ringmaster_intr_status0_r(void)
+{
+	return 0x00120058;
+}
+static inline u32 pri_ringmaster_intr_status1_r(void)
+{
+	return 0x0012005c;
+}
+static inline u32 pri_ringmaster_global_ctl_r(void)
+{
+	return 0x00120060;
+}
+static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void)
+{
+	return 0x1;
+}
+static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void)
+{
+	return 0x0;
+}
+static inline u32 pri_ringmaster_enum_fbp_r(void)
+{
+	return 0x00120074;
+}
+static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r)
+{
+	return (r >> 0) & 0x1f;
+}
+static inline u32 pri_ringmaster_enum_gpc_r(void)
+{
+	return 0x00120078;
+}
+static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r)
+{
+	return (r >> 0) & 0x1f;
+}
+static inline u32 pri_ringmaster_enum_ltc_r(void)
+{
+	return 0x0012006c;
+}
+static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r)
+{
+	return (r >> 0) & 0x1f;
+}
+#endif

drivers/gpu/nvgpu/gm206/hw_pri_ringstation_sys_gm206.h

@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pri_ringstation_sys_gm206_h_
+#define _hw_pri_ringstation_sys_gm206_h_
+
+static inline u32 pri_ringstation_sys_master_config_r(u32 i)
+{
+	return 0x00122300 + i*4;
+}
+static inline u32 pri_ringstation_sys_decode_config_r(void)
+{
+	return 0x00122204;
+}
+static inline u32 pri_ringstation_sys_decode_config_ring_m(void)
+{
+	return 0x7 << 0;
+}
+static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void)
+{
+	return 0x1;
+}
+#endif

drivers/gpu/nvgpu/gm206/hw_proj_gm206.h

@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_proj_gm206_h_
+#define _hw_proj_gm206_h_
+
+static inline u32 proj_gpc_base_v(void)
+{
+	return 0x00500000;
+}
+static inline u32 proj_gpc_shared_base_v(void)
+{
+	return 0x00418000;
+}
+static inline u32 proj_gpc_stride_v(void)
+{
+	return 0x00008000;
+}
+static inline u32 proj_ltc_stride_v(void)
+{
+	return 0x00002000;
+}
+static inline u32 proj_lts_stride_v(void)
+{
+	return 0x00000200;
+}
+static inline u32 proj_fbpa_stride_v(void)
+{
+	return 0x00004000;
+}
+static inline u32 proj_ppc_in_gpc_base_v(void)
+{
+	return 0x00003000;
+}
+static inline u32 proj_ppc_in_gpc_stride_v(void)
+{
+	return 0x00000200;
+}
+static inline u32 proj_rop_base_v(void)
+{
+	return 0x00410000;
+}
+static inline u32 proj_rop_shared_base_v(void)
+{
+	return 0x00408800;
+}
+static inline u32 proj_rop_stride_v(void)
+{
+	return 0x00000400;
+}
+static inline u32 proj_tpc_in_gpc_base_v(void)
+{
+	return 0x00004000;
+}
+static inline u32 proj_tpc_in_gpc_stride_v(void)
+{
+	return 0x00000800;
+}
+static inline u32 proj_tpc_in_gpc_shared_base_v(void)
+{
+	return 0x00001800;
+}
+static inline u32 proj_host_num_pbdma_v(void)
+{
+	return 0x00000003;
+}
+static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void)
+{
+	return 0x00000004;
+}
+static inline u32 proj_scal_litter_num_fbps_v(void)
+{
+	return 0x00000006;
+}
+static inline u32 proj_scal_litter_num_fbpas_v(void)
+{
+	return 0x00000006;
+}
+static inline u32 proj_scal_litter_num_gpcs_v(void)
+{
+	return 0x00000006;
+}
+static inline u32 proj_scal_litter_num_pes_per_gpc_v(void)
+{
+	return 0x00000002;
+}
+static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void)
+{
+	return 0x00000002;
+}
+static inline u32 proj_scal_litter_num_zcull_banks_v(void)
+{
+	return 0x00000004;
+}
+static inline u32 proj_scal_max_gpcs_v(void)
+{
+	return 0x00000020;
+}
+static inline u32 proj_scal_max_tpc_per_gpc_v(void)
+{
+	return 0x00000008;
+}
+#endif

drivers/gpu/nvgpu/gm206/hw_pwr_gm206.h

@@ -0,0 +1,825 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pwr_gm206_h_
+#define _hw_pwr_gm206_h_
+
+static inline u32 pwr_falcon_irqsset_r(void)
+{
+	return 0x0010a000;
+}
+static inline u32 pwr_falcon_irqsset_swgen0_set_f(void)
+{
+	return 0x40;
+}
+static inline u32 pwr_falcon_irqsclr_r(void)
+{
+	return 0x0010a004;
+}
+static inline u32 pwr_falcon_irqstat_r(void)
+{
+	return 0x0010a008;
+}
+static inline u32 pwr_falcon_irqstat_halt_true_f(void)
+{
+	return 0x10;
+}
+static inline u32 pwr_falcon_irqstat_exterr_true_f(void)
+{
+	return 0x20;
+}
+static inline u32 pwr_falcon_irqstat_swgen0_true_f(void)
+{
+	return 0x40;
+}
+static inline u32 pwr_falcon_irqmode_r(void)
+{
+	return 0x0010a00c;
+}
+static inline u32 pwr_falcon_irqmset_r(void)
+{
+	return 0x0010a010;
+}
+static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v)
+{
+	return (v & 0x1) << 1;
+}
+static inline u32 pwr_falcon_irqmset_mthd_f(u32 v)
+{
+	return (v & 0x1) << 2;
+}
+static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v)
+{
+	return (v & 0x1) << 3;
+}
+static inline u32 pwr_falcon_irqmset_halt_f(u32 v)
+{
+	return (v & 0x1) << 4;
+}
+static inline u32 pwr_falcon_irqmset_exterr_f(u32 v)
+{
+	return (v & 0x1) << 5;
+}
+static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v)
+{
+	return (v & 0x1) << 6;
+}
+static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v)
+{
+	return (v & 0x1) << 7;
+}
+static inline u32 pwr_falcon_irqmclr_r(void)
+{
+	return 0x0010a014;
+}
+static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v)
+{
+	return (v & 0x1) << 1;
+}
+static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v)
+{
+	return (v & 0x1) << 2;
+}
+static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v)
+{
+	return (v & 0x1) << 3;
+}
+static inline u32 pwr_falcon_irqmclr_halt_f(u32 v)
+{
+	return (v & 0x1) << 4;
+}
+static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v)
+{
+	return (v & 0x1) << 5;
+}
+static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v)
+{
+	return (v & 0x1) << 6;
+}
+static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v)
+{
+	return (v & 0x1) << 7;
+}
+static inline u32 pwr_falcon_irqmclr_ext_f(u32 v)
+{
+	return (v & 0xff) << 8;
+}
+static inline u32 pwr_falcon_irqmask_r(void)
+{
+	return 0x0010a018;
+}
+static inline u32 pwr_falcon_irqdest_r(void)
+{
+	return 0x0010a01c;
+}
+static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v)
+{
+	return (v & 0x1) << 1;
+}
+static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v)
+{
+	return (v & 0x1) << 2;
+}
+static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v)
+{
+	return (v & 0x1) << 3;
+}
+static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v)
+{
+	return (v & 0x1) << 4;
+}
+static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v)
+{
+	return (v & 0x1) << 5;
+}
+static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v)
+{
+	return (v & 0x1) << 6;
+}
+static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v)
+{
+	return (v & 0x1) << 7;
+}
+static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v)
+{
+	return (v & 0xff) << 8;
+}
+static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v)
+{
+	return (v & 0x1) << 16;
+}
+static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v)
+{
+	return (v & 0x1) << 17;
+}
+static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v)
+{
+	return (v & 0x1) << 18;
+}
+static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v)
+{
+	return (v & 0x1) << 19;
+}
+static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v)
+{
+	return (v & 0x1) << 20;
+}
+static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v)
+{
+	return (v & 0x1) << 21;
+}
+static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v)
+{
+	return (v & 0x1) << 22;
+}
+static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v)
+{
+	return (v & 0x1) << 23;
+}
+static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v)
+{
+	return (v & 0xff) << 24;
+}
+static inline u32 pwr_falcon_curctx_r(void)
+{
+	return 0x0010a050;
+}
+static inline u32 pwr_falcon_nxtctx_r(void)
+{
+	return 0x0010a054;
+}
+static inline u32 pwr_falcon_mailbox0_r(void)
+{
+	return 0x0010a040;
+}
+static inline u32 pwr_falcon_mailbox1_r(void)
+{
+	return 0x0010a044;
+}
+static inline u32 pwr_falcon_itfen_r(void)
+{
+	return 0x0010a048;
+}
+static inline u32 pwr_falcon_itfen_ctxen_enable_f(void)
+{
+	return 0x1;
+}
+static inline u32 pwr_falcon_idlestate_r(void)
+{
+	return 0x0010a04c;
+}
+static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r)
+{
+	return (r >> 0) & 0x1;
+}
+static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r)
+{
+	return (r >> 1) & 0x7fff;
+}
+static inline u32 pwr_falcon_os_r(void)
+{
+	return 0x0010a080;
+}
+static inline u32 pwr_falcon_engctl_r(void)
+{
+	return 0x0010a0a4;
+}
+static inline u32 pwr_falcon_cpuctl_r(void)
+{
+	return 0x0010a100;
+}
+static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v)
+{
+	return (v & 0x1) << 1;
+}
+static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v)
+{
+	return (v & 0x1) << 4;
+}
+static inline u32 pwr_falcon_cpuctl_halt_intr_m(void)
+{
+	return 0x1 << 4;
+}
+static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r)
+{
+	return (r >> 4) & 0x1;
+}
+static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
+{
+	return (v & 0x1) << 6;
+}
+static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void)
+{
+	return 0x1 << 6;
+}
+static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
+{
+	return (r >> 6) & 0x1;
+}
+static inline u32 pwr_falcon_cpuctl_alias_r(void)
+{
+	return 0x0010a130;
+}
+static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v)
+{
+	return (v & 0x1) << 1;
+}
+static inline u32 pwr_pmu_scpctl_stat_r(void)
+{
+	return 0x0010ac08;
+}
+static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v)
+{
+	return (v & 0x1) << 20;
+}
+static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void)
+{
+	return 0x1 << 20;
+}
+static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r)
+{
+	return (r >> 20) & 0x1;
+}
+static inline u32 pwr_falcon_imemc_r(u32 i)
+{
+	return 0x0010a180 + i*16;
+}
+static inline u32 pwr_falcon_imemc_offs_f(u32 v)
+{
+	return (v & 0x3f) << 2;
+}
+static inline u32 pwr_falcon_imemc_blk_f(u32 v)
+{
+	return (v & 0xff) << 8;
+}
+static inline u32 pwr_falcon_imemc_aincw_f(u32 v)
+{
+	return (v & 0x1) << 24;
+}
+static inline u32 pwr_falcon_imemd_r(u32 i)
+{
+	return 0x0010a184 + i*16;
+}
+static inline u32 pwr_falcon_imemt_r(u32 i)
+{
+	return 0x0010a188 + i*16;
+}
+static inline u32 pwr_falcon_sctl_r(void)
+{
+	return 0x0010a240;
+}
+static inline u32 pwr_falcon_mmu_phys_sec_r(void)
+{
+	return 0x00100ce4;
+}
+static inline u32 pwr_falcon_bootvec_r(void)
+{
+	return 0x0010a104;
+}
+static inline u32 pwr_falcon_bootvec_vec_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 pwr_falcon_dmactl_r(void)
+{
+	return 0x0010a10c;
+}
+static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void)
+{
+	return 0x1 << 1;
+}
+static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void)
+{
+	return 0x1 << 2;
+}
+static inline u32 pwr_falcon_dmactl_require_ctx_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 pwr_falcon_hwcfg_r(void)
+{
+	return 0x0010a108;
+}
+static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r)
+{
+	return (r >> 0) & 0x1ff;
+}
+static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r)
+{
+	return (r >> 9) & 0x1ff;
+}
+static inline u32 pwr_falcon_dmatrfbase_r(void)
+{
+	return 0x0010a110;
+}
+static inline u32 pwr_falcon_dmatrfmoffs_r(void)
+{
+	return 0x0010a114;
+}
+static inline u32 pwr_falcon_dmatrfcmd_r(void)
+{
+	return 0x0010a118;
+}
+static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v)
+{
+	return (v & 0x1) << 4;
+}
+static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v)
+{
+	return (v & 0x1) << 5;
+}
+static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v)
+{
+	return (v & 0x7) << 8;
+}
+static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v)
+{
+	return (v & 0x7) << 12;
+}
+static inline u32 pwr_falcon_dmatrffboffs_r(void)
+{
+	return 0x0010a11c;
+}
+static inline u32 pwr_falcon_exterraddr_r(void)
+{
+	return 0x0010a168;
+}
+static inline u32 pwr_falcon_exterrstat_r(void)
+{
+	return 0x0010a16c;
+}
+static inline u32 pwr_falcon_exterrstat_valid_m(void)
+{
+	return 0x1 << 31;
+}
+static inline u32 pwr_falcon_exterrstat_valid_v(u32 r)
+{
+	return (r >> 31) & 0x1;
+}
+static inline u32 pwr_falcon_exterrstat_valid_true_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_r(void)
+{
+	return 0x0010a200;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void)
+{
+	return 4;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v)
+{
+	return (v & 0xf) << 0;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void)
+{
+	return 0xf << 0;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r)
+{
+	return (r >> 0) & 0xf;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void)
+{
+	return 0x8;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void)
+{
+	return 0xe;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v)
+{
+	return (v & 0x1f) << 8;
+}
+static inline u32 pwr_pmu_falcon_icd_rdata_r(void)
+{
+	return 0x0010a20c;
+}
+static inline u32 pwr_falcon_dmemc_r(u32 i)
+{
+	return 0x0010a1c0 + i*8;
+}
+static inline u32 pwr_falcon_dmemc_offs_f(u32 v)
+{
+	return (v & 0x3f) << 2;
+}
+static inline u32 pwr_falcon_dmemc_offs_m(void)
+{
+	return 0x3f << 2;
+}
+static inline u32 pwr_falcon_dmemc_blk_f(u32 v)
+{
+	return (v & 0xff) << 8;
+}
+static inline u32 pwr_falcon_dmemc_blk_m(void)
+{
+	return 0xff << 8;
+}
+static inline u32 pwr_falcon_dmemc_aincw_f(u32 v)
+{
+	return (v & 0x1) << 24;
+}
+static inline u32 pwr_falcon_dmemc_aincr_f(u32 v)
+{
+	return (v & 0x1) << 25;
+}
+static inline u32 pwr_falcon_dmemd_r(u32 i)
+{
+	return 0x0010a1c4 + i*8;
+}
+static inline u32 pwr_pmu_new_instblk_r(void)
+{
+	return 0x0010a480;
+}
+static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v)
+{
+	return (v & 0xfffffff) << 0;
+}
+static inline u32 pwr_pmu_new_instblk_target_fb_f(void)
+{
+	return 0x0;
+}
+static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void)
+{
+	return 0x20000000;
+}
+static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void)
+{
+	return 0x30000000;
+}
+static inline u32 pwr_pmu_new_instblk_valid_f(u32 v)
+{
+	return (v & 0x1) << 30;
+}
+static inline u32 pwr_pmu_mutex_id_r(void)
+{
+	return 0x0010a488;
+}
+static inline u32 pwr_pmu_mutex_id_value_v(u32 r)
+{
+	return (r >> 0) & 0xff;
+}
+static inline u32 pwr_pmu_mutex_id_value_init_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void)
+{
+	return 0x000000ff;
+}
+static inline u32 pwr_pmu_mutex_id_release_r(void)
+{
+	return 0x0010a48c;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_m(void)
+{
+	return 0xff << 0;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_init_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_init_f(void)
+{
+	return 0x0;
+}
+static inline u32 pwr_pmu_mutex_r(u32 i)
+{
+	return 0x0010a580 + i*4;
+}
+static inline u32 pwr_pmu_mutex__size_1_v(void)
+{
+	return 0x00000010;
+}
+static inline u32 pwr_pmu_mutex_value_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 pwr_pmu_mutex_value_v(u32 r)
+{
+	return (r >> 0) & 0xff;
+}
+static inline u32 pwr_pmu_mutex_value_initial_lock_f(void)
+{
+	return 0x0;
+}
+static inline u32 pwr_pmu_queue_head_r(u32 i)
+{
+	return 0x0010a4a0 + i*4;
+}
+static inline u32 pwr_pmu_queue_head__size_1_v(void)
+{
+	return 0x00000004;
+}
+static inline u32 pwr_pmu_queue_head_address_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 pwr_pmu_queue_head_address_v(u32 r)
+{
+	return (r >> 0) & 0xffffffff;
+}
+static inline u32 pwr_pmu_queue_tail_r(u32 i)
+{
+	return 0x0010a4b0 + i*4;
+}
+static inline u32 pwr_pmu_queue_tail__size_1_v(void)
+{
+	return 0x00000004;
+}
+static inline u32 pwr_pmu_queue_tail_address_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 pwr_pmu_queue_tail_address_v(u32 r)
+{
+	return (r >> 0) & 0xffffffff;
+}
+static inline u32 pwr_pmu_msgq_head_r(void)
+{
+	return 0x0010a4c8;
+}
+static inline u32 pwr_pmu_msgq_head_val_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 pwr_pmu_msgq_head_val_v(u32 r)
+{
+	return (r >> 0) & 0xffffffff;
+}
+static inline u32 pwr_pmu_msgq_tail_r(void)
+{
+	return 0x0010a4cc;
+}
+static inline u32 pwr_pmu_msgq_tail_val_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 pwr_pmu_msgq_tail_val_v(u32 r)
+{
+	return (r >> 0) & 0xffffffff;
+}
+static inline u32 pwr_pmu_idle_mask_r(u32 i)
+{
+	return 0x0010a504 + i*16;
+}
+static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void)
+{
+	return 0x1;
+}
+static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void)
+{
+	return 0x200000;
+}
+static inline u32 pwr_pmu_idle_count_r(u32 i)
+{
+	return 0x0010a508 + i*16;
+}
+static inline u32 pwr_pmu_idle_count_value_f(u32 v)
+{
+	return (v & 0x7fffffff) << 0;
+}
+static inline u32 pwr_pmu_idle_count_value_v(u32 r)
+{
+	return (r >> 0) & 0x7fffffff;
+}
+static inline u32 pwr_pmu_idle_count_reset_f(u32 v)
+{
+	return (v & 0x1) << 31;
+}
+static inline u32 pwr_pmu_idle_ctrl_r(u32 i)
+{
+	return 0x0010a50c + i*16;
+}
+static inline u32 pwr_pmu_idle_ctrl_value_m(void)
+{
+	return 0x3 << 0;
+}
+static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void)
+{
+	return 0x2;
+}
+static inline u32 pwr_pmu_idle_ctrl_value_always_f(void)
+{
+	return 0x3;
+}
+static inline u32 pwr_pmu_idle_ctrl_filter_m(void)
+{
+	return 0x1 << 2;
+}
+static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void)
+{
+	return 0x0;
+}
+static inline u32 pwr_pmu_idle_mask_supp_r(u32 i)
+{
+	return 0x0010a9f0 + i*8;
+}
+static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i)
+{
+	return 0x0010a9f4 + i*8;
+}
+static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i)
+{
+	return 0x0010aa30 + i*8;
+}
+static inline u32 pwr_pmu_debug_r(u32 i)
+{
+	return 0x0010a5c0 + i*4;
+}
+static inline u32 pwr_pmu_debug__size_1_v(void)
+{
+	return 0x00000004;
+}
+static inline u32 pwr_pmu_mailbox_r(u32 i)
+{
+	return 0x0010a450 + i*4;
+}
+static inline u32 pwr_pmu_mailbox__size_1_v(void)
+{
+	return 0x0000000c;
+}
+static inline u32 pwr_pmu_bar0_addr_r(void)
+{
+	return 0x0010a7a0;
+}
+static inline u32 pwr_pmu_bar0_data_r(void)
+{
+	return 0x0010a7a4;
+}
+static inline u32 pwr_pmu_bar0_ctl_r(void)
+{
+	return 0x0010a7ac;
+}
+static inline u32 pwr_pmu_bar0_timeout_r(void)
+{
+	return 0x0010a7a8;
+}
+static inline u32 pwr_pmu_bar0_fecs_error_r(void)
+{
+	return 0x0010a988;
+}
+static inline u32 pwr_pmu_bar0_error_status_r(void)
+{
+	return 0x0010a7b0;
+}
+static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
+{
+	return 0x0010a6c0 + i*4;
+}
+static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i)
+{
+	return 0x0010a6e8 + i*4;
+}
+static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i)
+{
+	return 0x0010a710 + i*4;
+}
+static inline u32 pwr_pmu_pg_intren_r(u32 i)
+{
+	return 0x0010a760 + i*4;
+}
+static inline u32 pwr_fbif_transcfg_r(u32 i)
+{
+	return 0x0010ae00 + i*4;
+}
+static inline u32 pwr_fbif_transcfg_target_local_fb_f(void)
+{
+	return 0x0;
+}
+static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void)
+{
+	return 0x1;
+}
+static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void)
+{
+	return 0x2;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_s(void)
+{
+	return 1;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v)
+{
+	return (v & 0x1) << 2;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_m(void)
+{
+	return 0x1 << 2;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r)
+{
+	return (r >> 2) & 0x1;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void)
+{
+	return 0x0;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void)
+{
+	return 0x4;
+}
+#endif

drivers/gpu/nvgpu/gm206/hw_ram_gm206.h

@@ -0,0 +1,445 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ram_gm206_h_
+#define _hw_ram_gm206_h_
+
+static inline u32 ram_in_ramfc_s(void)
+{
+	return 4096;
+}
+static inline u32 ram_in_ramfc_w(void)
+{
+	return 0;
+}
+static inline u32 ram_in_page_dir_base_target_f(u32 v)
+{
+	return (v & 0x3) << 0;
+}
+static inline u32 ram_in_page_dir_base_target_w(void)
+{
+	return 128;
+}
+static inline u32 ram_in_page_dir_base_target_vid_mem_f(void)
+{
+	return 0x0;
+}
+static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void)
+{
+	return 0x2;
+}
+static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void)
+{
+	return 0x3;
+}
+static inline u32 ram_in_page_dir_base_vol_w(void)
+{
+	return 128;
+}
+static inline u32 ram_in_page_dir_base_vol_true_f(void)
+{
+	return 0x4;
+}
+static inline u32 ram_in_big_page_size_f(u32 v)
+{
+	return (v & 0x1) << 11;
+}
+static inline u32 ram_in_big_page_size_m(void)
+{
+	return 0x1 << 11;
+}
+static inline u32 ram_in_big_page_size_w(void)
+{
+	return 128;
+}
+static inline u32 ram_in_big_page_size_128kb_f(void)
+{
+	return 0x0;
+}
+static inline u32 ram_in_big_page_size_64kb_f(void)
+{
+	return 0x800;
+}
+static inline u32 ram_in_page_dir_base_lo_f(u32 v)
+{
+	return (v & 0xfffff) << 12;
+}
+static inline u32 ram_in_page_dir_base_lo_w(void)
+{
+	return 128;
+}
+static inline u32 ram_in_page_dir_base_hi_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 ram_in_page_dir_base_hi_w(void)
+{
+	return 129;
+}
+static inline u32 ram_in_adr_limit_lo_f(u32 v)
+{
+	return (v & 0xfffff) << 12;
+}
+static inline u32 ram_in_adr_limit_lo_w(void)
+{
+	return 130;
+}
+static inline u32 ram_in_adr_limit_hi_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 ram_in_adr_limit_hi_w(void)
+{
+	return 131;
+}
+static inline u32 ram_in_engine_cs_w(void)
+{
+	return 132;
+}
+static inline u32 ram_in_engine_cs_wfi_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 ram_in_engine_cs_wfi_f(void)
+{
+	return 0x0;
+}
+static inline u32 ram_in_engine_cs_fg_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ram_in_engine_cs_fg_f(void)
+{
+	return 0x8;
+}
+static inline u32 ram_in_gr_cs_w(void)
+{
+	return 132;
+}
+static inline u32 ram_in_gr_cs_wfi_f(void)
+{
+	return 0x0;
+}
+static inline u32 ram_in_gr_wfi_target_w(void)
+{
+	return 132;
+}
+static inline u32 ram_in_gr_wfi_mode_w(void)
+{
+	return 132;
+}
+static inline u32 ram_in_gr_wfi_mode_physical_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 ram_in_gr_wfi_mode_physical_f(void)
+{
+	return 0x0;
+}
+static inline u32 ram_in_gr_wfi_mode_virtual_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ram_in_gr_wfi_mode_virtual_f(void)
+{
+	return 0x4;
+}
+static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v)
+{
+	return (v & 0xfffff) << 12;
+}
+static inline u32 ram_in_gr_wfi_ptr_lo_w(void)
+{
+	return 132;
+}
+static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v)
+{
+	return (v & 0xff) << 0;
+}
+static inline u32 ram_in_gr_wfi_ptr_hi_w(void)
+{
+	return 133;
+}
+static inline u32 ram_in_base_shift_v(void)
+{
+	return 0x0000000c;
+}
+static inline u32 ram_in_alloc_size_v(void)
+{
+	return 0x00001000;
+}
+static inline u32 ram_fc_size_val_v(void)
+{
+	return 0x00000200;
+}
+static inline u32 ram_fc_gp_put_w(void)
+{
+	return 0;
+}
+static inline u32 ram_fc_userd_w(void)
+{
+	return 2;
+}
+static inline u32 ram_fc_userd_hi_w(void)
+{
+	return 3;
+}
+static inline u32 ram_fc_signature_w(void)
+{
+	return 4;
+}
+static inline u32 ram_fc_gp_get_w(void)
+{
+	return 5;
+}
+static inline u32 ram_fc_pb_get_w(void)
+{
+	return 6;
+}
+static inline u32 ram_fc_pb_get_hi_w(void)
+{
+	return 7;
+}
+static inline u32 ram_fc_pb_top_level_get_w(void)
+{
+	return 8;
+}
+static inline u32 ram_fc_pb_top_level_get_hi_w(void)
+{
+	return 9;
+}
+static inline u32 ram_fc_acquire_w(void)
+{
+	return 12;
+}
+static inline u32 ram_fc_semaphorea_w(void)
+{
+	return 14;
+}
+static inline u32 ram_fc_semaphoreb_w(void)
+{
+	return 15;
+}
+static inline u32 ram_fc_semaphorec_w(void)
+{
+	return 16;
+}
+static inline u32 ram_fc_semaphored_w(void)
+{
+	return 17;
+}
+static inline u32 ram_fc_gp_base_w(void)
+{
+	return 18;
+}
+static inline u32 ram_fc_gp_base_hi_w(void)
+{
+	return 19;
+}
+static inline u32 ram_fc_gp_fetch_w(void)
+{
+	return 20;
+}
+static inline u32 ram_fc_pb_fetch_w(void)
+{
+	return 21;
+}
+static inline u32 ram_fc_pb_fetch_hi_w(void)
+{
+	return 22;
+}
+static inline u32 ram_fc_pb_put_w(void)
+{
+	return 23;
+}
+static inline u32 ram_fc_pb_put_hi_w(void)
+{
+	return 24;
+}
+static inline u32 ram_fc_pb_header_w(void)
+{
+	return 33;
+}
+static inline u32 ram_fc_pb_count_w(void)
+{
+	return 34;
+}
+static inline u32 ram_fc_subdevice_w(void)
+{
+	return 37;
+}
+static inline u32 ram_fc_formats_w(void)
+{
+	return 39;
+}
+static inline u32 ram_fc_target_w(void)
+{
+	return 43;
+}
+static inline u32 ram_fc_hce_ctrl_w(void)
+{
+	return 57;
+}
+static inline u32 ram_fc_chid_w(void)
+{
+	return 58;
+}
+static inline u32 ram_fc_chid_id_f(u32 v)
+{
+	return (v & 0xfff) << 0;
+}
+static inline u32 ram_fc_chid_id_w(void)
+{
+	return 0;
+}
+static inline u32 ram_fc_runlist_timeslice_w(void)
+{
+	return 62;
+}
+static inline u32 ram_userd_base_shift_v(void)
+{
+	return 0x00000009;
+}
+static inline u32 ram_userd_chan_size_v(void)
+{
+	return 0x00000200;
+}
+static inline u32 ram_userd_put_w(void)
+{
+	return 16;
+}
+static inline u32 ram_userd_get_w(void)
+{
+	return 17;
+}
+static inline u32 ram_userd_ref_w(void)
+{
+	return 18;
+}
+static inline u32 ram_userd_put_hi_w(void)
+{
+	return 19;
+}
+static inline u32 ram_userd_ref_threshold_w(void)
+{
+	return 20;
+}
+static inline u32 ram_userd_top_level_get_w(void)
+{
+	return 22;
+}
+static inline u32 ram_userd_top_level_get_hi_w(void)
+{
+	return 23;
+}
+static inline u32 ram_userd_get_hi_w(void)
+{
+	return 24;
+}
+static inline u32 ram_userd_gp_get_w(void)
+{
+	return 34;
+}
+static inline u32 ram_userd_gp_put_w(void)
+{
+	return 35;
+}
+static inline u32 ram_userd_gp_top_level_get_w(void)
+{
+	return 22;
+}
+static inline u32 ram_userd_gp_top_level_get_hi_w(void)
+{
+	return 23;
+}
+static inline u32 ram_rl_entry_size_v(void)
+{
+	return 0x00000008;
+}
+static inline u32 ram_rl_entry_chid_f(u32 v)
+{
+	return (v & 0xfff) << 0;
+}
+static inline u32 ram_rl_entry_id_f(u32 v)
+{
+	return (v & 0xfff) << 0;
+}
+static inline u32 ram_rl_entry_type_f(u32 v)
+{
+	return (v & 0x1) << 13;
+}
+static inline u32 ram_rl_entry_type_chid_f(void)
+{
+	return 0x0;
+}
+static inline u32 ram_rl_entry_type_tsg_f(void)
+{
+	return 0x2000;
+}
+static inline u32 ram_rl_entry_timeslice_scale_f(u32 v)
+{
+	return (v & 0xf) << 14;
+}
+static inline u32 ram_rl_entry_timeslice_scale_3_f(void)
+{
+	return 0xc000;
+}
+static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v)
+{
+	return (v & 0xff) << 18;
+}
+static inline u32 ram_rl_entry_timeslice_timeout_128_f(void)
+{
+	return 0x2000000;
+}
+static inline u32 ram_rl_entry_tsg_length_f(u32 v)
+{
+	return (v & 0x3f) << 26;
+}
+#endif

drivers/gpu/nvgpu/gm206/hw_timer_gm206.h

@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_timer_gm206_h_
+#define _hw_timer_gm206_h_
+
+static inline u32 timer_pri_timeout_r(void)
+{
+	return 0x00009080;
+}
+static inline u32 timer_pri_timeout_period_f(u32 v)
+{
+	return (v & 0xffffff) << 0;
+}
+static inline u32 timer_pri_timeout_period_m(void)
+{
+	return 0xffffff << 0;
+}
+static inline u32 timer_pri_timeout_period_v(u32 r)
+{
+	return (r >> 0) & 0xffffff;
+}
+static inline u32 timer_pri_timeout_en_f(u32 v)
+{
+	return (v & 0x1) << 31;
+}
+static inline u32 timer_pri_timeout_en_m(void)
+{
+	return 0x1 << 31;
+}
+static inline u32 timer_pri_timeout_en_v(u32 r)
+{
+	return (r >> 31) & 0x1;
+}
+static inline u32 timer_pri_timeout_en_en_enabled_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 timer_pri_timeout_en_en_disabled_f(void)
+{
+	return 0x0;
+}
+static inline u32 timer_pri_timeout_save_0_r(void)
+{
+	return 0x00009084;
+}
+static inline u32 timer_pri_timeout_save_1_r(void)
+{
+	return 0x00009088;
+}
+static inline u32 timer_pri_timeout_fecs_errcode_r(void)
+{
+	return 0x0000908c;
+}
+static inline u32 timer_time_0_r(void)
+{
+	return 0x00009400;
+}
+static inline u32 timer_time_1_r(void)
+{
+	return 0x00009410;
+}
+#endif

drivers/gpu/nvgpu/gm206/hw_top_gm206.h

@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_top_gm206_h_
+#define _hw_top_gm206_h_
+
+static inline u32 top_num_gpcs_r(void)
+{
+	return 0x00022430;
+}
+static inline u32 top_num_gpcs_value_v(u32 r)
+{
+	return (r >> 0) & 0x1f;
+}
+static inline u32 top_tpc_per_gpc_r(void)
+{
+	return 0x00022434;
+}
+static inline u32 top_tpc_per_gpc_value_v(u32 r)
+{
+	return (r >> 0) & 0x1f;
+}
+static inline u32 top_num_fbps_r(void)
+{
+	return 0x00022438;
+}
+static inline u32 top_num_fbps_value_v(u32 r)
+{
+	return (r >> 0) & 0x1f;
+}
+static inline u32 top_ltc_per_fbp_r(void)
+{
+	return 0x00022450;
+}
+static inline u32 top_ltc_per_fbp_value_v(u32 r)
+{
+	return (r >> 0) & 0x1f;
+}
+static inline u32 top_slices_per_ltc_r(void)
+{
+	return 0x0002245c;
+}
+static inline u32 top_slices_per_ltc_value_v(u32 r)
+{
+	return (r >> 0) & 0x1f;
+}
+static inline u32 top_num_ltcs_r(void)
+{
+	return 0x00022454;
+}
+static inline u32 top_device_info_r(u32 i)
+{
+	return 0x00022700 + i*4;
+}
+static inline u32 top_device_info__size_1_v(void)
+{
+	return 0x00000040;
+}
+static inline u32 top_device_info_chain_v(u32 r)
+{
+	return (r >> 31) & 0x1;
+}
+static inline u32 top_device_info_chain_enable_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 top_device_info_engine_enum_v(u32 r)
+{
+	return (r >> 26) & 0xf;
+}
+static inline u32 top_device_info_runlist_enum_v(u32 r)
+{
+	return (r >> 21) & 0xf;
+}
+static inline u32 top_device_info_intr_enum_v(u32 r)
+{
+	return (r >> 15) & 0x1f;
+}
+static inline u32 top_device_info_reset_enum_v(u32 r)
+{
+	return (r >> 9) & 0x1f;
+}
+static inline u32 top_device_info_type_enum_v(u32 r)
+{
+	return (r >> 2) & 0x1fffffff;
+}
+static inline u32 top_device_info_type_enum_graphics_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 top_device_info_type_enum_graphics_f(void)
+{
+	return 0x0;
+}
+static inline u32 top_device_info_type_enum_copy0_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 top_device_info_type_enum_copy0_f(void)
+{
+	return 0x4;
+}
+static inline u32 top_device_info_entry_v(u32 r)
+{
+	return (r >> 0) & 0x3;
+}
+static inline u32 top_device_info_entry_not_valid_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 top_device_info_entry_enum_v(void)
+{
+	return 0x00000002;
+}
+static inline u32 top_scratch1_r(void)
+{
+	return 0x0002240c;
+}
+static inline u32 top_scratch1_devinit_completed_v(u32 r)
+{
+	return (r >> 1) & 0x1;
+}
+#endif

drivers/gpu/nvgpu/gm206/hw_xve_gm206.h

@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_xve_gm206_h_
+#define _hw_xve_gm206_h_
+
+static inline u32 xve_rom_ctrl_r(void)
+{
+	return 0x00000050;
+}
+static inline u32 xve_rom_ctrl_rom_shadow_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 xve_rom_ctrl_rom_shadow_disabled_f(void)
+{
+	return 0x0;
+}
+static inline u32 xve_rom_ctrl_rom_shadow_enabled_f(void)
+{
+	return 0x1;
+}
+#endif

include/uapi/linux/nvgpu.h

@@ -86,6 +86,8 @@ struct nvgpu_gpu_zbc_query_table_args {
 #define NVGPU_GPU_IMPL_GK20A 0x0000000A
 
 #define NVGPU_GPU_ARCH_GM200 0x00000120
+#define NVGPU_GPU_IMPL_GM204 0x00000004
+#define NVGPU_GPU_IMPL_GM206 0x00000006
 #define NVGPU_GPU_IMPL_GM20B 0x0000000B
 
 #ifdef CONFIG_ARCH_TEGRA_18x_SOC