gpu: nvgpu: Replace nvgpu_engine_info with nvgpu_device

Delete the struct nvgpu_engine_info as it's essentially identical to
struct nvgpu_device. Duplicating data structures is not ideal as it's
terribly confusing what does what.

Update all uses of nvgpu_engine_info to use struct nvgpu_device. This
is often a fairly straight forward replacement. Couple of places though
where things got interesting:

  - The enum_type that engine_info uses is defined in engines.h and
    has a bit of SW abstraction - in particular the GRCE type. The only
    place this seemed to be actually relevant (the IOCTL providing device
    info to userspace) the GRCE engines can be worked out by comparing
    runlist ID.
  - Addition of masks based on intr_id and reset_id; those can be
    computed easily enough using BIT32() but this is an area that
    could be improved on.

This reaches into a lot of extraneous code that traverses the fifo
active engines list and dramtically simplifies this. Now, instead of
having to go through a table of engine IDs that point to the list of
all host engines, the active engine list is just a list of pointers to
valid engines. It's now trivial to do a for-all-active-engines type
loop. This could even be turned into a generic macro or otherwise
abstracted in the future.

JIRA NVGPU-5421

Change-Id: I3a810deb55a7dd8c09836fd2dae85d3e28eb23cf
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2319895
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/ce/ce.c

@@ -23,6 +23,7 @@
 #include <nvgpu/types.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/engines.h>
+#include <nvgpu/device.h>
 #include <nvgpu/ce.h>
 #include <nvgpu/power_features/cg.h>
 #include <nvgpu/gops_mc.h>
@@ -41,16 +42,11 @@ int nvgpu_ce_init_support(struct gk20a *g)
 
 #if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
 	if (g->ops.mc.reset_engine != NULL) {
-		err = nvgpu_next_mc_reset_engine(g, NVGPU_ENGINE_GRCE);
+		err = nvgpu_next_mc_reset_engine(g, NVGPU_DEVTYPE_LCE);
 		if (err != 0) {
 			nvgpu_err(g, "NVGPU_ENGINE_GRCE reset failed");
 			return err;
 		}
-		err = nvgpu_next_mc_reset_engine(g, NVGPU_ENGINE_ASYNC_CE);
-		if (err != 0) {
-			nvgpu_err(g, "NVGPU_ENGINE_ASYNC_CE reset failed");
-			return err;
-		}
 	} else {
 #endif
 	ce_reset_mask = nvgpu_engine_get_all_ce_reset_mask(g);

drivers/gpu/nvgpu/common/device.c

@@ -121,16 +121,17 @@ int nvgpu_device_init(struct gk20a *g)
 {
 	u32 i;
 
+	device_dbg(g, "Initializating GPU device list");
+
 	/*
 	 * Ground work - make sure we aren't doing this again and that we have
 	 * all the necessary data structures.
 	 */
 	if (g->devs != NULL) {
+		device_dbg(g, "  GPU device list already present. Done.");
 		return 0;
 	}
 
-	device_dbg(g, "Initializating GPU device list");
-
 	g->devs = nvgpu_kzalloc(g, sizeof(*g->devs));
 	if (g->devs == NULL) {
 		return -ENOMEM;
@@ -162,10 +163,13 @@ void nvgpu_device_cleanup(struct gk20a *g)
 	u32 i;
 	struct nvgpu_list_node *devlist;
 
+	device_dbg(g, "Releasing GPU device list");
+
 	/*
 	 * Make unit testing a bit easier.
 	 */
 	if (g->devs == NULL) {
+		device_dbg(g, "  Already done.");
 		return;
 	}
 
@@ -193,14 +197,12 @@ void nvgpu_device_cleanup(struct gk20a *g)
 static const struct nvgpu_device *dev_instance_from_devlist(
 	struct nvgpu_list_node *devlist, u32 inst_id)
 {
-	u32 i = 0U;
 	struct nvgpu_device *dev;
 
 	nvgpu_list_for_each_entry(dev, devlist, nvgpu_device, dev_list_node) {
-		if (inst_id == i) {
+		if (dev->inst_id == inst_id) {
 			return dev;
 		}
-		i++;
 	}
 
 	return NULL;

drivers/gpu/nvgpu/common/fifo/runlist.c

@@ -24,6 +24,7 @@
 #include <nvgpu/channel.h>
 #include <nvgpu/fifo.h>
 #include <nvgpu/engines.h>
+#include <nvgpu/device.h>
 #include <nvgpu/runlist.h>
 #include <nvgpu/ptimer.h>
 #include <nvgpu/bug.h>
@@ -681,8 +682,8 @@ void nvgpu_runlist_cleanup_sw(struct gk20a *g)
 void nvgpu_runlist_init_enginfo(struct gk20a *g, struct nvgpu_fifo *f)
 {
 	struct nvgpu_runlist_info *runlist;
-	struct nvgpu_engine_info *engine_info;
-	u32 i, engine_id, j;
+	const struct nvgpu_device *dev;
+	u32 i, j;
 
 	nvgpu_log_fn(g, " ");
 
@@ -700,11 +701,10 @@ void nvgpu_runlist_init_enginfo(struct gk20a *g, struct nvgpu_fifo *f)
 				 runlist->runlist_id, runlist->pbdma_bitmask);
 
 		for (j = 0; j < f->num_engines; j++) {
-			engine_id = f->active_engines_list[j];
-			engine_info = &f->engine_info[engine_id];
+			dev = f->active_engines[j];
 
-			if (engine_info->runlist_id == runlist->runlist_id) {
-				runlist->eng_bitmask |= BIT32(engine_id);
+			if (dev->runlist_id == runlist->runlist_id) {
+				runlist->eng_bitmask |= BIT32(dev->engine_id);
 			}
 		}
 		nvgpu_log(g, gpu_dbg_info, "runlist %d: act eng bitmask 0x%x",

drivers/gpu/nvgpu/common/gr/gr.c

@@ -44,6 +44,7 @@
 #include <nvgpu/power_features/cg.h>
 #include <nvgpu/power_features/pg.h>
 #include <nvgpu/mc.h>
+#include <nvgpu/device.h>
 #include <nvgpu/gops_mc.h>
 #if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
 #include <nvgpu/engines.h>
@@ -665,7 +666,7 @@ static int gr_init_prepare_hw(struct gk20a *g)
 	if (g->ops.mc.reset_engine != NULL) {
 		g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_PERFMON));
 
-		err = nvgpu_next_mc_reset_engine(g, NVGPU_ENGINE_GR);
+		err = nvgpu_next_mc_reset_engine(g, NVGPU_DEVTYPE_GRAPHICS);
 		if (err != 0) {
 			nvgpu_err(g, "NVGPU_ENGINE_GR reset failed");
 			return err;

drivers/gpu/nvgpu/common/init/nvgpu_init.c

@@ -900,6 +900,12 @@ static void gk20a_free_cb(struct nvgpu_ref *refcount)
 		g->ops.ltc.ltc_remove_support(g);
 	}
 
+	/*
+	 * Free the device list once the gk20a struct is removed. We don't want
+	 * to do this during the railgate poweroff sequence since that means
+	 * that the device list disappears every time we rail-gate. That will
+	 * cause the fifo engine code to explode.
+	 */
 	nvgpu_device_cleanup(g);
 
 #ifdef CONFIG_NVGPU_PROFILER

drivers/gpu/nvgpu/common/nvlink/nvlink.c

@@ -26,6 +26,7 @@
 #include <nvgpu/enabled.h>
 #include <nvgpu/device.h>
 #include <nvgpu/nvlink_bios.h>
+#include <nvgpu/device.h>
 
 #ifdef CONFIG_NVGPU_NVLINK
 
@@ -156,8 +157,8 @@ fail:
 static int nvgpu_nvlink_discover_ioctrl(struct gk20a *g)
 {
 	u32 i;
-	struct nvgpu_nvlink_ioctrl_list *ioctrl_table;
 	u32 ioctrl_num_entries = 0U;
+	struct nvgpu_nvlink_ioctrl_list *ioctrl_table;
 
 	ioctrl_num_entries = nvgpu_device_count(g, NVGPU_DEVTYPE_IOCTRL);
 	nvgpu_log_info(g, "ioctrl_num_entries: %d", ioctrl_num_entries);

drivers/gpu/nvgpu/common/power_features/cg/cg.c

@@ -22,6 +22,7 @@
 
 #include <nvgpu/gk20a.h>
 #include <nvgpu/engines.h>
+#include <nvgpu/device.h>
 #include <nvgpu/enabled.h>
 #include <nvgpu/power_features/cg.h>
 
@@ -29,22 +30,18 @@ static void nvgpu_cg_set_mode(struct gk20a *g, u32 cgmode, u32 mode_config)
 {
 	u32 n;
 	u32 engine_id = 0;
-#ifdef CONFIG_NVGPU_NON_FUSA
-	struct nvgpu_engine_info *engine_info = NULL;
-#endif
+	const struct nvgpu_device *dev = NULL;
 	struct nvgpu_fifo *f = &g->fifo;
 
 	nvgpu_log_fn(g, " ");
 
 	for (n = 0; n < f->num_engines; n++) {
-		engine_id = f->active_engines_list[n];
+		dev = f->active_engines[n];
 
 #ifdef CONFIG_NVGPU_NON_FUSA
-		engine_info = &f->engine_info[engine_id];
-
 		/* gr_engine supports both BLCG and ELCG */
-		if ((cgmode == BLCG_MODE) && (engine_info->engine_enum ==
-						NVGPU_ENGINE_GR)) {
+		if ((cgmode == BLCG_MODE) &&
+		    (dev->type == NVGPU_DEVTYPE_GRAPHICS)) {
 			g->ops.therm.init_blcg_mode(g, (u32)mode_config,
 						engine_id);
 			break;
@@ -52,7 +49,7 @@ static void nvgpu_cg_set_mode(struct gk20a *g, u32 cgmode, u32 mode_config)
 #endif
 		if (cgmode == ELCG_MODE) {
 			g->ops.therm.init_elcg_mode(g, (u32)mode_config,
-						engine_id);
+						dev->engine_id);
 		} else {
 			nvgpu_err(g, "invalid cg mode %d, config %d for "
 							"engine_id %d",

drivers/gpu/nvgpu/common/vgpu/fifo/fifo_vgpu.c

@@ -47,6 +47,19 @@
 
 void vgpu_fifo_cleanup_sw(struct gk20a *g)
 {
+	u32 i;
+	struct nvgpu_fifo *f = &g->fifo;
+
+	for (i = 0U; i < f->max_engines; i++) {
+		if (f->host_engines[i] == NULL) {
+			continue;
+		}
+
+		/*
+		 * Cast to (void *) to get rid of the constness.
+		 */
+		nvgpu_kfree(g, (void *)f->host_engines[i]);
+	}
 	nvgpu_fifo_cleanup_sw_common(g);
 }
 

drivers/gpu/nvgpu/common/vgpu/top/top_vgpu.c

@@ -54,6 +54,7 @@ struct nvgpu_device *vgpu_top_parse_next_dev(struct gk20a *g, u32 *token)
 	/*
 	 * Copy the engine data into the device and return it to our caller.
 	 */
+	dev->type       = engines->info[*token].engine_enum;
 	dev->engine_id  = engines->info[*token].engine_id;
 	dev->intr_id    = nvgpu_ffs(engines->info[*token].intr_mask) - 1;
 	dev->reset_id   = nvgpu_ffs(engines->info[*token].reset_mask) - 1;
@@ -63,29 +64,6 @@ struct nvgpu_device *vgpu_top_parse_next_dev(struct gk20a *g, u32 *token)
 	dev->pri_base   = engines->info[*token].pri_base;
 	dev->fault_id   = engines->info[*token].fault_id;
 
-	/*
-	 * vGPU sends us an engine enum; this'll be fixed once we remove
-	 * the engine_info struct. For now just do a quick reverse map.
-	 *
-	 * GRCEs and ASYNC_CEs are both LCEs in terms of engine types.
-	 */
-	switch (engines->info[*token].engine_enum) {
-	case NVGPU_ENGINE_GR:
-		dev->type = NVGPU_DEVTYPE_GRAPHICS;
-		break;
-	case NVGPU_ENGINE_GRCE:
-		dev->type = NVGPU_DEVTYPE_LCE;
-		break;
-	case NVGPU_ENGINE_ASYNC_CE:
-		dev->type = NVGPU_DEVTYPE_LCE;
-		break;
-	default:
-		nvgpu_err(g, "Unknown engine_enum: %d",
-			  engines->info[*token].engine_enum);
-		nvgpu_assert(true);
-		break;
-	}
-
 	(*token)++;
 
 	return dev;