gpu: nvgpu: Replace nvgpu_engine_info with nvgpu_device

Delete the struct nvgpu_engine_info as it's essentially identical to
struct nvgpu_device. Duplicating data structures is not ideal as it's
terribly confusing what does what.

Update all uses of nvgpu_engine_info to use struct nvgpu_device. This
is often a fairly straight forward replacement. Couple of places though
where things got interesting:

  - The enum_type that engine_info uses is defined in engines.h and
    has a bit of SW abstraction - in particular the GRCE type. The only
    place this seemed to be actually relevant (the IOCTL providing device
    info to userspace) the GRCE engines can be worked out by comparing
    runlist ID.
  - Addition of masks based on intr_id and reset_id; those can be
    computed easily enough using BIT32() but this is an area that
    could be improved on.

This reaches into a lot of extraneous code that traverses the fifo
active engines list and dramtically simplifies this. Now, instead of
having to go through a table of engine IDs that point to the list of
all host engines, the active engine list is just a list of pointers to
valid engines. It's now trivial to do a for-all-active-engines type
loop. This could even be turned into a generic macro or otherwise
abstracted in the future.

JIRA NVGPU-5421

Change-Id: I3a810deb55a7dd8c09836fd2dae85d3e28eb23cf
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2319895
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Alex Waterman
2020-05-19 16:41:41 -05:00
parent df9695bd13
commit fba96fdc09
38 changed files with 597 additions and 929 deletions

View File

@@ -36,6 +36,7 @@
#include <nvgpu/clk_arb.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/engines.h>
#include <nvgpu/device.h>
#include <nvgpu/gr/config.h>
#ifdef CONFIG_NVGPU_GRAPHICS
#include <nvgpu/gr/zbc.h>
@@ -1009,46 +1010,43 @@ static int nvgpu_gpu_get_engine_info(
struct nvgpu_gpu_get_engine_info_args *args)
{
int err = 0;
u32 engine_enum = NVGPU_ENGINE_INVAL;
u32 report_index = 0;
u32 engine_id_idx;
u32 i;
const struct nvgpu_device *gr_dev;
const u32 max_buffer_engines = args->engine_info_buf_size /
sizeof(struct nvgpu_gpu_get_engine_info_item);
struct nvgpu_gpu_get_engine_info_item __user *dst_item_list =
(void __user *)(uintptr_t)args->engine_info_buf_addr;
for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines;
++engine_id_idx) {
u32 active_engine_id = g->fifo.active_engines_list[engine_id_idx];
const struct nvgpu_engine_info *src_info =
&g->fifo.engine_info[active_engine_id];
gr_dev = nvgpu_device_get(g, NVGPU_DEVTYPE_GRAPHICS, 0);
nvgpu_assert(gr_dev != NULL);
for (i = 0; i < g->fifo.num_engines; i++) {
const struct nvgpu_device *dev = g->fifo.active_engines[i];
struct nvgpu_gpu_get_engine_info_item dst_info;
(void) memset(&dst_info, 0, sizeof(dst_info));
engine_enum = src_info->engine_enum;
switch (engine_enum) {
case NVGPU_ENGINE_GR:
if (nvgpu_device_is_graphics(g, dev)) {
dst_info.engine_id = NVGPU_GPU_ENGINE_ID_GR;
break;
case NVGPU_ENGINE_GRCE:
dst_info.engine_id = NVGPU_GPU_ENGINE_ID_GR_COPY;
break;
case NVGPU_ENGINE_ASYNC_CE:
dst_info.engine_id = NVGPU_GPU_ENGINE_ID_ASYNC_COPY;
break;
default:
nvgpu_err(g, "Unmapped engine enum %u",
engine_enum);
continue;
} else if (nvgpu_device_is_ce(g, dev)) {
/*
* There's two types of CE userpsace is interested in:
* ASYNC_CEs which are copy engines with their own
* runlists and GRCEs which are CEs that share a runlist
* with GR.
*/
if (dev->runlist_id == gr_dev->runlist_id) {
dst_info.engine_id =
NVGPU_GPU_ENGINE_ID_GR_COPY;
} else {
dst_info.engine_id =
NVGPU_GPU_ENGINE_ID_ASYNC_COPY;
}
}
dst_info.engine_instance = src_info->inst_id;
dst_info.runlist_id = src_info->runlist_id;
dst_info.engine_instance = dev->inst_id;
dst_info.runlist_id = dev->runlist_id;
if (report_index < max_buffer_engines) {
err = copy_to_user(&dst_item_list[report_index],