gpu: nvgpu: Remove fifo->pbdma_map

The FIFO pbdma map is an array of bit maps that link PBDMAs to runlists.
This array allows other software to query what PBDMA(s) serves a given
runlist. The PBDMA map is read verbatim from an array of host registers.
These registers are stored in a kmalloc()'ed array.

This causes a problem for the device management code. The device
management initialization executes well before the rest of the FIFO
PBDMA initialization occurs. Thus, if the device management code
queries the PBDMA mapping for a given device/runlist, the mapping has
yet to be populated.

In the next patches in this series the engine management code is subsumed
into the device management code. In other words the device struct is
reused by the engine management and all host SW does is pull pointers to
the host managed devices from the device manager. This means that all
engine initialization that used to be done on top of the device
management needs to move to the device code.

So, long story short, the PBDMA map needs to be read from the registers
directly, instead of an array that gets allocated long after the device
code has run.

This patch removes the pbdma map array, deletes two HALs that managed
that, and instead provides a new HAL to query this map directly from
the registers so that the device code can use it.

JIRA NVGPU-5421

Change-Id: I5966d440903faee640e3b41494d2caf4cd177b6d
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2361134
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit

userspace/required_tests.ini

@@ -405,7 +405,7 @@ test_gv11b_mm_mmu_fault_setup_hw.setup_hw=0
 test_gv11b_mm_mmu_fault_setup_sw.setup_sw_s0=0
 test_gv11b_mm_mmu_fault_setup_sw.setup_sw_s1=0
 test_handle_mmu_fault_common.handle_mmu_common_s0=0
-test_handle_mmu_fault_common.handle_mmu_common_s10=0
+test_handle_mmu_fault_common.handle_mmu_common_s10=2
 test_handle_mmu_fault_common.handle_mmu_common_s1=0
 test_handle_mmu_fault_common.handle_mmu_common_s2=0
 test_handle_mmu_fault_common.handle_mmu_common_s3=0
@@ -587,7 +587,6 @@ test_gk20a_fifo_intr_handle_chsw_error.intr_handle_chsw_error=0
 test_gk20a_fifo_intr_handle_runlist_event.intr_handle_runlist_event=0
 test_gk20a_fifo_pbdma_isr.pbdma_isr=0
 test_gk20a_get_timeslices.get_timeslices=0
-test_gk20a_init_pbdma_map.init_pbdma_map=0
 
 [nvgpu_fifo_gv11b]
 test_fifo_init_support.init_support=0
@@ -690,7 +689,6 @@ test_nvgpu_memset_sysmem.nvgpu_memset_sysmem=0
 [nvgpu_pbdma]
 test_fifo_init_support.init_support=0
 test_fifo_remove_support.remove_support=0
-test_pbdma_find_for_runlist.pbdma_find_for_runlist=0
 test_pbdma_setup_sw.setup_sw=0
 test_pbdma_status.pbdma_status=0
 

userspace/units/fifo/engine/nvgpu-engine.c

@@ -173,15 +173,8 @@ done:
 
 #define F_ENGINE_INIT_INFO_GET_DEV_INFO_NULL	BIT(0)
 #define F_ENGINE_INIT_INFO_GET_DEV_INFO_FAIL	BIT(1)
-#define F_ENGINE_INIT_INFO_PBDMA_FIND_FAIL	BIT(2)
-#define F_ENGINE_INIT_INFO_INIT_CE_FAIL		BIT(3)
-#define F_ENGINE_INIT_INFO_LAST			BIT(4)
-
-static bool stub_pbdma_find_for_runlist_none(struct gk20a *g,
-			u32 runlist_id, u32 *pbdma_id)
-{
-	return false;
-}
+#define F_ENGINE_INIT_INFO_INIT_CE_FAIL		BIT(2)
+#define F_ENGINE_INIT_INFO_LAST			BIT(3)
 
 static int stub_engine_init_ce_info_EINVAL(struct nvgpu_fifo *f)
 {
@@ -200,12 +193,10 @@ int test_engine_init_info(struct unit_module *m,
 	u32 fail =
 		F_ENGINE_INIT_INFO_GET_DEV_INFO_NULL |
 		F_ENGINE_INIT_INFO_GET_DEV_INFO_FAIL |
-		F_ENGINE_INIT_INFO_PBDMA_FIND_FAIL |
 		F_ENGINE_INIT_INFO_INIT_CE_FAIL;
 	const char *labels[] = {
 		"get_dev_info_null",
 		"get_dev_info_fail",
-		"pbdma_find_fail",
 		"init_ce_fail",
 	};
 	u32 prune = fail;
@@ -221,11 +212,6 @@ int test_engine_init_info(struct unit_module *m,
 		unit_verbose(m, "%s branches=%s\n", __func__,
 			branches_str(branches, labels));
 
-		g->ops.pbdma.find_for_runlist =
-			branches & F_ENGINE_INIT_INFO_PBDMA_FIND_FAIL ?
-				stub_pbdma_find_for_runlist_none :
-				gops.pbdma.find_for_runlist;
-
 		g->ops.engine.init_ce_info =
 			branches & F_ENGINE_INIT_INFO_INIT_CE_FAIL ?
 				stub_engine_init_ce_info_EINVAL :

userspace/units/fifo/fifo/gk20a/nvgpu-fifo-gk20a.c

@@ -58,28 +58,6 @@
 
 #define UNIT_MAX_PBDMA	32
 
-int test_gk20a_init_pbdma_map(struct unit_module *m,
-		struct gk20a *g, void *args)
-{
-	int ret = UNIT_FAIL;
-	u32 num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA);
-	u32 pbdma_map[UNIT_MAX_PBDMA];
-	u32 id;
-	unit_assert(num_pbdma > 0, goto done);
-	unit_assert(num_pbdma <= UNIT_MAX_PBDMA, goto done);
-
-	memset(pbdma_map, 0, sizeof(pbdma_map));
-	gk20a_fifo_init_pbdma_map(g, pbdma_map, num_pbdma);
-	for (id = 0; id < num_pbdma; id++) {
-		unit_verbose(m, "id=%u map=%08x\n", id, pbdma_map[id]);
-		unit_assert(pbdma_map[id] != 0, goto done);
-	}
-
-	ret = UNIT_SUCCESS;
-done:
-	return ret;
-}
-
 int test_gk20a_get_timeslices(struct unit_module *m,
 		struct gk20a *g, void *args)
 {
@@ -106,7 +84,6 @@ struct unit_module_test nvgpu_fifo_gk20a_tests[] = {
 	UNIT_TEST(init_support, test_fifo_init_support, NULL, 0),
 
 	/* fifo gk20a */
-	UNIT_TEST(init_pbdma_map, test_gk20a_init_pbdma_map, NULL, 0),
 	UNIT_TEST(get_timeslices, test_gk20a_get_timeslices, NULL, 0),
 
 	/* fifo intr gk20a */

userspace/units/fifo/pbdma/gm20b/nvgpu-pbdma-gm20b.c

@@ -418,10 +418,11 @@ int test_gm20b_pbdma_read_data(struct unit_module *m,
 		struct gk20a *g, void *args)
 {
 	int ret = UNIT_FAIL;
-	struct nvgpu_fifo *f = &g->fifo;
 	u32 pbdma_id = 0;
 
-	for (pbdma_id = 0; pbdma_id < f->num_pbdma; pbdma_id++) {
+	for (pbdma_id = 0;
+	     pbdma_id < nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA);
+	     pbdma_id++) {
 		u32 pattern = (0xbeef << 16) + pbdma_id;
 		nvgpu_writel(g, pbdma_hdr_shadow_r(pbdma_id), pattern);
 		unit_assert(gm20b_pbdma_read_data(g, pbdma_id) == pattern,

userspace/units/fifo/pbdma/nvgpu-pbdma.c

@@ -64,11 +64,10 @@ struct unit_ctx {
 
 static struct unit_ctx unit_ctx;
 
-#define F_PBDMA_SETUP_SW_KZALLOC_FAIL		BIT(0)
-#define F_PBDMA_SETUP_SW_DEVICE_FATAL_0		BIT(1)
-#define F_PBDMA_SETUP_SW_CHANNEL_FATAL_0	BIT(2)
-#define F_PBDMA_SETUP_SW_RESTARTABLE_0		BIT(3)
-#define F_PBDMA_SETUP_SW_LAST			BIT(4)
+#define F_PBDMA_SETUP_SW_DEVICE_FATAL_0		BIT(0)
+#define F_PBDMA_SETUP_SW_CHANNEL_FATAL_0	BIT(1)
+#define F_PBDMA_SETUP_SW_RESTARTABLE_0		BIT(2)
+#define F_PBDMA_SETUP_SW_LAST			BIT(3)
 
 static u32 stub_pbdma_device_fatal_0_intr_descs(void) {
 	return F_PBDMA_SETUP_SW_DEVICE_FATAL_0;
@@ -90,14 +89,12 @@ int test_pbdma_setup_sw(struct unit_module *m,
 	struct nvgpu_posix_fault_inj *kmem_fi;
 	u32 branches = 0U;
 	int ret = UNIT_FAIL;
-	u32 fail = F_PBDMA_SETUP_SW_KZALLOC_FAIL;
 	static const char *labels[] = {
-		"kzalloc_fail",
 		"device_fatal_0",
 		"channel_fatal_0",
 		"restartable_0",
 	};
-	u32 prune = fail;
+	u32 prune = 0U;
 	int err;
 
 	kmem_fi = nvgpu_kmem_get_fault_injection();
@@ -117,10 +114,6 @@ int test_pbdma_setup_sw(struct unit_module *m,
 		unit_verbose(m, "%s branches=%s\n", __func__,
 			branches_str(branches, labels));
 
-		nvgpu_posix_enable_fault_injection(kmem_fi,
-			branches & F_PBDMA_SETUP_SW_KZALLOC_FAIL ?
-				true : false, 0);
-
 		f->intr.pbdma.device_fatal_0 = 0;
 		f->intr.pbdma.channel_fatal_0 = 0;
 		f->intr.pbdma.restartable_0 = 0;
@@ -139,24 +132,18 @@ int test_pbdma_setup_sw(struct unit_module *m,
 
 		err = nvgpu_pbdma_setup_sw(g);
 
-		if (branches & fail) {
-			unit_assert(err != 0, goto done);
-			unit_assert(f->pbdma_map == NULL, goto done);
-		} else {
-			unit_assert(err == 0, goto done);
-			unit_assert(f->pbdma_map != NULL, goto done);
-			unit_assert(f->intr.pbdma.device_fatal_0 ==
-				(branches & F_PBDMA_SETUP_SW_DEVICE_FATAL_0),
-				goto done);
-			unit_assert(f->intr.pbdma.channel_fatal_0 ==
-				(branches & F_PBDMA_SETUP_SW_CHANNEL_FATAL_0),
-				goto done);
-			unit_assert(f->intr.pbdma.restartable_0 ==
-				(branches & F_PBDMA_SETUP_SW_RESTARTABLE_0),
-				goto done);
-			nvgpu_pbdma_cleanup_sw(g);
-			unit_assert(f->pbdma_map == NULL, goto done);
-		}
+		unit_assert(err == 0, goto done);
+		unit_assert(f->intr.pbdma.device_fatal_0 ==
+			    (branches & F_PBDMA_SETUP_SW_DEVICE_FATAL_0),
+			    goto done);
+		unit_assert(f->intr.pbdma.channel_fatal_0 ==
+			    (branches & F_PBDMA_SETUP_SW_CHANNEL_FATAL_0),
+			    goto done);
+		unit_assert(f->intr.pbdma.restartable_0 ==
+			    (branches & F_PBDMA_SETUP_SW_RESTARTABLE_0),
+			    goto done);
+
+		nvgpu_pbdma_cleanup_sw(g);
 	}
 	ret = UNIT_SUCCESS;
 
@@ -170,46 +157,6 @@ done:
 	return ret;
 }
 
-int test_pbdma_find_for_runlist(struct unit_module *m,
-		struct gk20a *g, void *args)
-{
-	struct nvgpu_fifo *f = &g->fifo;
-	struct nvgpu_fifo fifo = g->fifo;
-	u32 runlist_id;
-	bool active;
-	bool found;
-	u32 pbdma_id;
-	int ret = UNIT_FAIL;
-
-	for (runlist_id = 0; runlist_id < f->max_runlists; runlist_id++) {
-
-		active = nvgpu_engine_is_valid_runlist_id(g, runlist_id);
-
-		pbdma_id = U32_MAX;
-		found = nvgpu_pbdma_find_for_runlist(g, runlist_id, &pbdma_id);
-
-		if (active) {
-			unit_assert(found, goto done);
-			unit_assert(pbdma_id != U32_MAX, goto done);
-			unit_assert((f->pbdma_map[pbdma_id] &
-				BIT(runlist_id)) != 0, goto done);
-		} else {
-			unit_assert(!found, goto done);
-			unit_assert(pbdma_id == U32_MAX, goto done);
-		}
-	}
-
-	f->num_pbdma = 0;
-	unit_assert(!nvgpu_pbdma_find_for_runlist(g, 0, &pbdma_id), goto done);
-
-	ret = UNIT_SUCCESS;
-
-done:
-	g->fifo = fifo;
-
-	return ret;
-}
-
 int test_pbdma_status(struct unit_module *m,
 		struct gk20a *g, void *args)
 {
@@ -264,7 +211,6 @@ done:
 struct unit_module_test nvgpu_pbdma_tests[] = {
 	UNIT_TEST(setup_sw, test_pbdma_setup_sw, &unit_ctx, 0),
 	UNIT_TEST(init_support, test_fifo_init_support, &unit_ctx, 0),
-	UNIT_TEST(pbdma_find_for_runlist, test_pbdma_find_for_runlist, &unit_ctx, 0),
 	UNIT_TEST(pbdma_status, test_pbdma_status, &unit_ctx, 0),
 	UNIT_TEST(remove_support, test_fifo_remove_support, &unit_ctx, 0),
 };

userspace/units/fifo/pbdma/nvgpu-pbdma.h

@@ -61,30 +61,6 @@ struct gk20a;
 int test_pbdma_setup_sw(struct unit_module *m,
 		struct gk20a *g, void *args);
 
-/**
- * Test specification for: test_pbdma_find_for_runlist
- *
- * Description: Branch coverage for nvgpu_pbdma_find_for_runlist
- *
- * Test Type: Feature
- *
- * Targets: nvgpu_pbdma_find_for_runlist, nvgpu_engine_is_valid_runlist_id
- *
- * Input: test_fifo_init_support() run for this GPU.
- *
- * Steps:
- * - Check that nvgpu_pbdma_find_for_runlist does not find any valid
- *   PBDMA for inactive runlists.
- * - Check that nvgpu_pbdma_find_for_runlist finds a valid PBDMA for
- *   active runlists:
- *   - Function must return true for active runlists.
- *   - Check PBDMA actually services the runlist using pbdma_map.
- *
- * Output: Returns PASS if all branches gave expected results. FAIL otherwise.
- */
-int test_pbdma_find_for_runlist(struct unit_module *m,
-		struct gk20a *g, void *args);
-
 /**
  * Test specification for: test_pbdma_status
  *

userspace/units/mc/nvgpu-mc.c

@@ -138,12 +138,6 @@ static void reset_ctx(void)
 	u.priv_ring_isr = false;
 }
 
-static bool mock_pbdma_find_for_runlist(struct gk20a *g, u32 runlist_id,
-					u32 *pbdma_id)
-{
-	return true;
-}
-
 static void mock_bus_isr(struct gk20a *g)
 {
 	u.bus_isr = true;
@@ -230,7 +224,6 @@ int test_setup_env(struct unit_module *m,
 	}
 
 	/* override HALs */
-	g->ops.pbdma.find_for_runlist = mock_pbdma_find_for_runlist;
 	g->ops.bus.isr = mock_bus_isr;
 	g->ops.ce.isr_stall = mock_ce_stall_isr;
 	g->ops.ce.isr_nonstall = mock_ce_nonstall_isr;

userspace/units/mm/hal/mmu_fault/gv11b_fusa/mmu-fault-gv11b-fusa.c

@@ -826,7 +826,7 @@ struct unit_module_test mm_mmu_fault_gv11b_fusa_tests[] = {
 	UNIT_TEST(handle_mmu_common_s7, test_handle_mmu_fault_common, (void *)F_MMU_HANDLER_NON_REPLAYABLE_REFCH, 0),
 	UNIT_TEST(handle_mmu_common_s8, test_handle_mmu_fault_common, (void *)F_MMU_HANDLER_NON_REPLAYABLE_REFCH_NACK_HNDLD, 0),
 	UNIT_TEST(handle_mmu_common_s9, test_handle_mmu_fault_common, (void *)F_MMU_HANDLER_NON_REPLAYABLE_FAULTED_INVALID, 0),
-	UNIT_TEST(handle_mmu_common_s10, test_handle_mmu_fault_common, (void *)F_MMU_HANDLER_NON_REPLAYABLE_TSG, 0),
+	UNIT_TEST(handle_mmu_common_s10, test_handle_mmu_fault_common, (void *)F_MMU_HANDLER_NON_REPLAYABLE_TSG, 2),
 	UNIT_TEST(handle_nonreplay_s0, test_handle_nonreplay_replay_fault, (void *)F_HANDLE_NON_RPLYBLE_BUF_EMPTY, 0),
 	UNIT_TEST(handle_nonreplay_s1, test_handle_nonreplay_replay_fault, (void *)F_HANDLE_NON_RPLYBLE_INVALID_BUF_ENTRY, 0),
 	UNIT_TEST(handle_nonreplay_s2, test_handle_nonreplay_replay_fault, (void *)F_HANDLE_NON_RPLYBLE_VALID_BUF_ENTRY, 0),