From fd332ca6b4450be78371d2e87b7c659c2a572ddb Mon Sep 17 00:00:00 2001 From: Sagar Kamble Date: Mon, 19 Nov 2018 16:12:13 +0530 Subject: [PATCH] gpu: nvgpu: s/*_flcn_*/*_falcon_* There is mixed usage of falcon & flcn in function and data types. Lets update all with "falcon" for consistency with file names. JIRA NVGPU-1459 Change-Id: I02dbc866ce2cca009f2e8b87cfe11a919ec10749 Signed-off-by: Sagar Kamble Reviewed-on: https://git-master.nvidia.com/r/1953793 Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/falcon/falcon.c | 64 ++++++++--------- .../gpu/nvgpu/common/falcon/falcon_gk20a.c | 48 ++++++------- .../gpu/nvgpu/common/falcon/falcon_queue.c | 72 +++++++++---------- drivers/gpu/nvgpu/common/fb/fb_gv100.c | 20 +++--- drivers/gpu/nvgpu/common/pmu/acr_gm20b.c | 6 +- drivers/gpu/nvgpu/common/pmu/pmu.c | 18 ++--- drivers/gpu/nvgpu/common/pmu/pmu_debug.c | 4 +- drivers/gpu/nvgpu/common/pmu/pmu_gk20a.c | 12 ++-- drivers/gpu/nvgpu/common/pmu/pmu_gm20b.c | 8 +-- drivers/gpu/nvgpu/common/pmu/pmu_gp106.c | 4 +- drivers/gpu/nvgpu/common/pmu/pmu_gp10b.c | 2 +- drivers/gpu/nvgpu/common/pmu/pmu_gv11b.c | 4 +- drivers/gpu/nvgpu/common/pmu/pmu_ipc.c | 20 +++--- drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c | 2 +- drivers/gpu/nvgpu/common/sec2/sec2.c | 4 +- drivers/gpu/nvgpu/common/sec2/sec2_ipc.c | 16 ++--- drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 2 +- drivers/gpu/nvgpu/gp106/bios_gp106.c | 16 ++--- drivers/gpu/nvgpu/gp106/sec2_gp106.c | 4 +- drivers/gpu/nvgpu/gv100/gsp_gv100.c | 4 +- drivers/gpu/nvgpu/gv100/nvlink_gv100.c | 16 ++--- drivers/gpu/nvgpu/include/nvgpu/falcon.h | 72 +++++++++---------- drivers/gpu/nvgpu/os/linux/gk20a.c | 10 +-- drivers/gpu/nvgpu/tu104/sec2_tu104.c | 12 ++-- 24 files changed, 220 insertions(+), 220 deletions(-) diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c index a46adba3b..b200b0be7 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon.c @@ -31,7 +31,7 @@ #define MEM_SCRUBBING_TIMEOUT_MAX 1000 #define MEM_SCRUBBING_TIMEOUT_DEFAULT 10 -int nvgpu_flcn_wait_idle(struct nvgpu_falcon *flcn) +int nvgpu_falcon_wait_idle(struct nvgpu_falcon *flcn) { struct gk20a *g = flcn->g; struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; @@ -64,7 +64,7 @@ int nvgpu_flcn_wait_idle(struct nvgpu_falcon *flcn) return 0; } -int nvgpu_flcn_mem_scrub_wait(struct nvgpu_falcon *flcn) +int nvgpu_falcon_mem_scrub_wait(struct nvgpu_falcon *flcn) { struct nvgpu_timeout timeout; int status = 0; @@ -75,7 +75,7 @@ int nvgpu_flcn_mem_scrub_wait(struct nvgpu_falcon *flcn) MEM_SCRUBBING_TIMEOUT_DEFAULT, NVGPU_TIMER_RETRY_TIMER); do { - if (nvgpu_flcn_get_mem_scrubbing_status(flcn)) { + if (nvgpu_falcon_get_mem_scrubbing_status(flcn)) { goto exit; } nvgpu_udelay(MEM_SCRUBBING_TIMEOUT_DEFAULT); @@ -89,14 +89,14 @@ exit: return status; } -int nvgpu_flcn_reset(struct nvgpu_falcon *flcn) +int nvgpu_falcon_reset(struct nvgpu_falcon *flcn) { int status = 0; if (flcn->flcn_ops.reset != NULL) { status = flcn->flcn_ops.reset(flcn); if (status == 0) { - status = nvgpu_flcn_mem_scrub_wait(flcn); + status = nvgpu_falcon_mem_scrub_wait(flcn); } } else { nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ", @@ -107,7 +107,7 @@ int nvgpu_flcn_reset(struct nvgpu_falcon *flcn) return status; } -void nvgpu_flcn_set_irq(struct nvgpu_falcon *flcn, bool enable, +void nvgpu_falcon_set_irq(struct nvgpu_falcon *flcn, bool enable, u32 intr_mask, u32 intr_dest) { struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; @@ -122,7 +122,7 @@ void nvgpu_flcn_set_irq(struct nvgpu_falcon *flcn, bool enable, } } -bool nvgpu_flcn_get_mem_scrubbing_status(struct nvgpu_falcon *flcn) +bool nvgpu_falcon_get_mem_scrubbing_status(struct nvgpu_falcon *flcn) { struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; bool status = false; @@ -137,7 +137,7 @@ bool nvgpu_flcn_get_mem_scrubbing_status(struct nvgpu_falcon *flcn) return status; } -bool nvgpu_flcn_get_cpu_halted_status(struct nvgpu_falcon *flcn) +bool nvgpu_falcon_get_cpu_halted_status(struct nvgpu_falcon *flcn) { struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; bool status = false; @@ -152,7 +152,7 @@ bool nvgpu_flcn_get_cpu_halted_status(struct nvgpu_falcon *flcn) return status; } -int nvgpu_flcn_wait_for_halt(struct nvgpu_falcon *flcn, unsigned int timeout) +int nvgpu_falcon_wait_for_halt(struct nvgpu_falcon *flcn, unsigned int timeout) { struct gk20a *g = flcn->g; struct nvgpu_timeout to; @@ -160,7 +160,7 @@ int nvgpu_flcn_wait_for_halt(struct nvgpu_falcon *flcn, unsigned int timeout) nvgpu_timeout_init(g, &to, timeout, NVGPU_TIMER_CPU_TIMER); do { - if (nvgpu_flcn_get_cpu_halted_status(flcn)) { + if (nvgpu_falcon_get_cpu_halted_status(flcn)) { break; } @@ -174,7 +174,7 @@ int nvgpu_flcn_wait_for_halt(struct nvgpu_falcon *flcn, unsigned int timeout) return status; } -int nvgpu_flcn_clear_halt_intr_status(struct nvgpu_falcon *flcn, +int nvgpu_falcon_clear_halt_intr_status(struct nvgpu_falcon *flcn, unsigned int timeout) { struct gk20a *g = flcn->g; @@ -204,7 +204,7 @@ int nvgpu_flcn_clear_halt_intr_status(struct nvgpu_falcon *flcn, return status; } -bool nvgpu_flcn_get_idle_status(struct nvgpu_falcon *flcn) +bool nvgpu_falcon_get_idle_status(struct nvgpu_falcon *flcn) { struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; bool status = false; @@ -219,7 +219,7 @@ bool nvgpu_flcn_get_idle_status(struct nvgpu_falcon *flcn) return status; } -int nvgpu_flcn_copy_from_emem(struct nvgpu_falcon *flcn, +int nvgpu_falcon_copy_from_emem(struct nvgpu_falcon *flcn, u32 src, u8 *dst, u32 size, u8 port) { struct nvgpu_falcon_engine_dependency_ops *flcn_dops = @@ -233,7 +233,7 @@ int nvgpu_flcn_copy_from_emem(struct nvgpu_falcon *flcn, return status; } -int nvgpu_flcn_copy_to_emem(struct nvgpu_falcon *flcn, +int nvgpu_falcon_copy_to_emem(struct nvgpu_falcon *flcn, u32 dst, u8 *src, u32 size, u8 port) { struct nvgpu_falcon_engine_dependency_ops *flcn_dops = @@ -247,7 +247,7 @@ int nvgpu_flcn_copy_to_emem(struct nvgpu_falcon *flcn, return status; } -int nvgpu_flcn_copy_from_dmem(struct nvgpu_falcon *flcn, +int nvgpu_falcon_copy_from_dmem(struct nvgpu_falcon *flcn, u32 src, u8 *dst, u32 size, u8 port) { struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; @@ -255,7 +255,7 @@ int nvgpu_flcn_copy_from_dmem(struct nvgpu_falcon *flcn, return flcn_ops->copy_from_dmem(flcn, src, dst, size, port); } -int nvgpu_flcn_copy_to_dmem(struct nvgpu_falcon *flcn, +int nvgpu_falcon_copy_to_dmem(struct nvgpu_falcon *flcn, u32 dst, u8 *src, u32 size, u8 port) { struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; @@ -263,7 +263,7 @@ int nvgpu_flcn_copy_to_dmem(struct nvgpu_falcon *flcn, return flcn_ops->copy_to_dmem(flcn, dst, src, size, port); } -int nvgpu_flcn_copy_from_imem(struct nvgpu_falcon *flcn, +int nvgpu_falcon_copy_from_imem(struct nvgpu_falcon *flcn, u32 src, u8 *dst, u32 size, u8 port) { struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; @@ -279,7 +279,7 @@ int nvgpu_flcn_copy_from_imem(struct nvgpu_falcon *flcn, return status; } -int nvgpu_flcn_copy_to_imem(struct nvgpu_falcon *flcn, +int nvgpu_falcon_copy_to_imem(struct nvgpu_falcon *flcn, u32 dst, u8 *src, u32 size, u8 port, bool sec, u32 tag) { struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; @@ -296,8 +296,8 @@ int nvgpu_flcn_copy_to_imem(struct nvgpu_falcon *flcn, return status; } -static void nvgpu_flcn_print_mem(struct nvgpu_falcon *flcn, u32 src, - u32 size, enum flcn_mem_type mem_type) +static void nvgpu_falcon_print_mem(struct nvgpu_falcon *flcn, u32 src, + u32 size, enum falcon_mem_type mem_type) { u32 buff[64] = {0}; u32 total_block_read = 0; @@ -317,10 +317,10 @@ static void nvgpu_flcn_print_mem(struct nvgpu_falcon *flcn, u32 src, } if (mem_type == MEM_DMEM) { - status = nvgpu_flcn_copy_from_dmem(flcn, src, + status = nvgpu_falcon_copy_from_dmem(flcn, src, (u8 *)buff, byte_read_count, 0); } else { - status = nvgpu_flcn_copy_from_imem(flcn, src, + status = nvgpu_falcon_copy_from_imem(flcn, src, (u8 *)buff, byte_read_count, 0); } @@ -340,19 +340,19 @@ static void nvgpu_flcn_print_mem(struct nvgpu_falcon *flcn, u32 src, } while (total_block_read-- != 0U); } -void nvgpu_flcn_print_dmem(struct nvgpu_falcon *flcn, u32 src, u32 size) +void nvgpu_falcon_print_dmem(struct nvgpu_falcon *flcn, u32 src, u32 size) { nvgpu_info(flcn->g, " PRINT DMEM "); - nvgpu_flcn_print_mem(flcn, src, size, MEM_DMEM); + nvgpu_falcon_print_mem(flcn, src, size, MEM_DMEM); } -void nvgpu_flcn_print_imem(struct nvgpu_falcon *flcn, u32 src, u32 size) +void nvgpu_falcon_print_imem(struct nvgpu_falcon *flcn, u32 src, u32 size) { nvgpu_info(flcn->g, " PRINT IMEM "); - nvgpu_flcn_print_mem(flcn, src, size, MEM_IMEM); + nvgpu_falcon_print_mem(flcn, src, size, MEM_IMEM); } -int nvgpu_flcn_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector) +int nvgpu_falcon_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector) { struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; int status = -EINVAL; @@ -367,7 +367,7 @@ int nvgpu_flcn_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector) return status; } -u32 nvgpu_flcn_mailbox_read(struct nvgpu_falcon *flcn, u32 mailbox_index) +u32 nvgpu_falcon_mailbox_read(struct nvgpu_falcon *flcn, u32 mailbox_index) { struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; u32 data = 0; @@ -382,7 +382,7 @@ u32 nvgpu_flcn_mailbox_read(struct nvgpu_falcon *flcn, u32 mailbox_index) return data; } -void nvgpu_flcn_mailbox_write(struct nvgpu_falcon *flcn, u32 mailbox_index, +void nvgpu_falcon_mailbox_write(struct nvgpu_falcon *flcn, u32 mailbox_index, u32 data) { struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; @@ -395,7 +395,7 @@ void nvgpu_flcn_mailbox_write(struct nvgpu_falcon *flcn, u32 mailbox_index, } } -void nvgpu_flcn_dump_stats(struct nvgpu_falcon *flcn) +void nvgpu_falcon_dump_stats(struct nvgpu_falcon *flcn) { struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; @@ -407,7 +407,7 @@ void nvgpu_flcn_dump_stats(struct nvgpu_falcon *flcn) } } -int nvgpu_flcn_bl_bootstrap(struct nvgpu_falcon *flcn, +int nvgpu_falcon_bl_bootstrap(struct nvgpu_falcon *flcn, struct nvgpu_falcon_bl_info *bl_info) { struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; @@ -425,7 +425,7 @@ int nvgpu_flcn_bl_bootstrap(struct nvgpu_falcon *flcn, return status; } -int nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id) +int nvgpu_falcon_sw_init(struct gk20a *g, u32 flcn_id) { struct nvgpu_falcon *flcn = NULL; struct gpu_ops *gops = &g->ops; diff --git a/drivers/gpu/nvgpu/common/falcon/falcon_gk20a.c b/drivers/gpu/nvgpu/common/falcon/falcon_gk20a.c index 6f9a6ab0a..9e41ecd43 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon_gk20a.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon_gk20a.c @@ -28,7 +28,7 @@ #include -static int gk20a_flcn_reset(struct nvgpu_falcon *flcn) +static int gk20a_falcon_reset(struct nvgpu_falcon *flcn) { struct gk20a *g = flcn->g; u32 base_addr = flcn->flcn_base; @@ -49,7 +49,7 @@ static int gk20a_flcn_reset(struct nvgpu_falcon *flcn) return status; } -static bool gk20a_flcn_clear_halt_interrupt_status(struct nvgpu_falcon *flcn) +static bool gk20a_falcon_clear_halt_interrupt_status(struct nvgpu_falcon *flcn) { struct gk20a *g = flcn->g; u32 base_addr = flcn->flcn_base; @@ -70,7 +70,7 @@ static bool gk20a_flcn_clear_halt_interrupt_status(struct nvgpu_falcon *flcn) return status; } -static void gk20a_flcn_set_irq(struct nvgpu_falcon *flcn, bool enable) +static void gk20a_falcon_set_irq(struct nvgpu_falcon *flcn, bool enable) { struct gk20a *g = flcn->g; u32 base_addr = flcn->flcn_base; @@ -144,7 +144,7 @@ static bool gk20a_is_falcon_scrubbing_done(struct nvgpu_falcon *flcn) } static u32 gk20a_falcon_get_mem_size(struct nvgpu_falcon *flcn, - enum flcn_mem_type mem_type) + enum falcon_mem_type mem_type) { struct gk20a *g = flcn->g; u32 mem_size = 0; @@ -162,8 +162,8 @@ static u32 gk20a_falcon_get_mem_size(struct nvgpu_falcon *flcn, return mem_size; } -static int flcn_mem_overflow_check(struct nvgpu_falcon *flcn, - u32 offset, u32 size, enum flcn_mem_type mem_type) +static int falcon_mem_overflow_check(struct nvgpu_falcon *flcn, + u32 offset, u32 size, enum falcon_mem_type mem_type) { struct gk20a *g = flcn->g; u32 mem_size = 0; @@ -190,7 +190,7 @@ static int flcn_mem_overflow_check(struct nvgpu_falcon *flcn, return 0; } -static int gk20a_flcn_copy_from_dmem(struct nvgpu_falcon *flcn, +static int gk20a_falcon_copy_from_dmem(struct nvgpu_falcon *flcn, u32 src, u8 *dst, u32 size, u8 port) { struct gk20a *g = flcn->g; @@ -201,7 +201,7 @@ static int gk20a_flcn_copy_from_dmem(struct nvgpu_falcon *flcn, nvgpu_log_fn(g, " src dmem offset - %x, size - %x", src, size); - if (flcn_mem_overflow_check(flcn, src, size, MEM_DMEM) != 0) { + if (falcon_mem_overflow_check(flcn, src, size, MEM_DMEM) != 0) { nvgpu_err(g, "incorrect parameters"); return -EINVAL; } @@ -235,7 +235,7 @@ static int gk20a_flcn_copy_from_dmem(struct nvgpu_falcon *flcn, return 0; } -static int gk20a_flcn_copy_to_dmem(struct nvgpu_falcon *flcn, +static int gk20a_falcon_copy_to_dmem(struct nvgpu_falcon *flcn, u32 dst, u8 *src, u32 size, u8 port) { struct gk20a *g = flcn->g; @@ -246,7 +246,7 @@ static int gk20a_flcn_copy_to_dmem(struct nvgpu_falcon *flcn, nvgpu_log_fn(g, "dest dmem offset - %x, size - %x", dst, size); - if (flcn_mem_overflow_check(flcn, dst, size, MEM_DMEM) != 0) { + if (falcon_mem_overflow_check(flcn, dst, size, MEM_DMEM) != 0) { nvgpu_err(g, "incorrect parameters"); return -EINVAL; } @@ -290,7 +290,7 @@ static int gk20a_flcn_copy_to_dmem(struct nvgpu_falcon *flcn, return 0; } -static int gk20a_flcn_copy_from_imem(struct nvgpu_falcon *flcn, u32 src, +static int gk20a_falcon_copy_from_imem(struct nvgpu_falcon *flcn, u32 src, u8 *dst, u32 size, u8 port) { struct gk20a *g = flcn->g; @@ -304,7 +304,7 @@ static int gk20a_flcn_copy_from_imem(struct nvgpu_falcon *flcn, u32 src, nvgpu_log_info(g, "download %d bytes from 0x%x", size, src); - if (flcn_mem_overflow_check(flcn, src, size, MEM_IMEM) != 0) { + if (falcon_mem_overflow_check(flcn, src, size, MEM_IMEM) != 0) { nvgpu_err(g, "incorrect parameters"); return -EINVAL; } @@ -340,7 +340,7 @@ static int gk20a_flcn_copy_from_imem(struct nvgpu_falcon *flcn, u32 src, return 0; } -static int gk20a_flcn_copy_to_imem(struct nvgpu_falcon *flcn, u32 dst, +static int gk20a_falcon_copy_to_imem(struct nvgpu_falcon *flcn, u32 dst, u8 *src, u32 size, u8 port, bool sec, u32 tag) { struct gk20a *g = flcn->g; @@ -352,7 +352,7 @@ static int gk20a_flcn_copy_to_imem(struct nvgpu_falcon *flcn, u32 dst, nvgpu_log_info(g, "upload %d bytes to 0x%x", size, dst); - if (flcn_mem_overflow_check(flcn, dst, size, MEM_IMEM) != 0) { + if (falcon_mem_overflow_check(flcn, dst, size, MEM_IMEM) != 0) { nvgpu_err(g, "incorrect parameters"); return -EINVAL; } @@ -458,7 +458,7 @@ static int gk20a_falcon_bl_bootstrap(struct nvgpu_falcon *flcn, int err = 0; /*copy bootloader interface structure to dmem*/ - err = gk20a_flcn_copy_to_dmem(flcn, 0, (u8 *)bl_info->bl_desc, + err = gk20a_falcon_copy_to_dmem(flcn, 0, (u8 *)bl_info->bl_desc, bl_info->bl_desc_size, (u8)0); if (err != 0) { goto exit; @@ -468,7 +468,7 @@ static int gk20a_falcon_bl_bootstrap(struct nvgpu_falcon *flcn, dst = (falcon_falcon_hwcfg_imem_size_v(gk20a_readl(g, base_addr + falcon_falcon_hwcfg_r())) << 8) - bl_info->bl_size; - err = gk20a_flcn_copy_to_imem(flcn, dst, (u8 *)(bl_info->bl_src), + err = gk20a_falcon_copy_to_imem(flcn, dst, (u8 *)(bl_info->bl_src), bl_info->bl_size, (u8)0, false, bl_info->bl_start_tag); if (err != 0) { goto exit; @@ -676,7 +676,7 @@ static void gk20a_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn) break; default: /* NULL assignment make sure - * CPU hard reset in gk20a_flcn_reset() gets execute + * CPU hard reset in gk20a_falcon_reset() gets execute * if falcon doesn't need specific reset implementation */ flcn_eng_dep_ops->reset_eng = NULL; @@ -688,17 +688,17 @@ void gk20a_falcon_ops(struct nvgpu_falcon *flcn) { struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; - flcn_ops->reset = gk20a_flcn_reset; - flcn_ops->set_irq = gk20a_flcn_set_irq; + flcn_ops->reset = gk20a_falcon_reset; + flcn_ops->set_irq = gk20a_falcon_set_irq; flcn_ops->clear_halt_interrupt_status = - gk20a_flcn_clear_halt_interrupt_status; + gk20a_falcon_clear_halt_interrupt_status; flcn_ops->is_falcon_cpu_halted = gk20a_is_falcon_cpu_halted; flcn_ops->is_falcon_idle = gk20a_is_falcon_idle; flcn_ops->is_falcon_scrubbing_done = gk20a_is_falcon_scrubbing_done; - flcn_ops->copy_from_dmem = gk20a_flcn_copy_from_dmem; - flcn_ops->copy_to_dmem = gk20a_flcn_copy_to_dmem; - flcn_ops->copy_to_imem = gk20a_flcn_copy_to_imem; - flcn_ops->copy_from_imem = gk20a_flcn_copy_from_imem; + flcn_ops->copy_from_dmem = gk20a_falcon_copy_from_dmem; + flcn_ops->copy_to_dmem = gk20a_falcon_copy_to_dmem; + flcn_ops->copy_to_imem = gk20a_falcon_copy_to_imem; + flcn_ops->copy_from_imem = gk20a_falcon_copy_from_imem; flcn_ops->bootstrap = gk20a_falcon_bootstrap; flcn_ops->dump_falcon_stats = gk20a_falcon_dump_stats; flcn_ops->mailbox_read = gk20a_falcon_mailbox_read; diff --git a/drivers/gpu/nvgpu/common/falcon/falcon_queue.c b/drivers/gpu/nvgpu/common/falcon/falcon_queue.c index 084136907..888cb6b35 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon_queue.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon_queue.c @@ -26,7 +26,7 @@ #include /* common falcon queue ops */ -static int flcn_queue_head(struct nvgpu_falcon *flcn, +static int falcon_queue_head(struct nvgpu_falcon *flcn, struct nvgpu_falcon_queue *queue, u32 *head, bool set) { int err = -ENOSYS; @@ -39,7 +39,7 @@ static int flcn_queue_head(struct nvgpu_falcon *flcn, return err; } -static int flcn_queue_tail(struct nvgpu_falcon *flcn, +static int falcon_queue_tail(struct nvgpu_falcon *flcn, struct nvgpu_falcon_queue *queue, u32 *tail, bool set) { int err = -ENOSYS; @@ -52,7 +52,7 @@ static int flcn_queue_tail(struct nvgpu_falcon *flcn, return err; } -static bool flcn_queue_has_room(struct nvgpu_falcon *flcn, +static bool falcon_queue_has_room(struct nvgpu_falcon *flcn, struct nvgpu_falcon_queue *queue, u32 size, bool *need_rewind) { u32 q_head = 0; @@ -97,7 +97,7 @@ exit: return size <= q_free; } -static int flcn_queue_rewind(struct nvgpu_falcon *flcn, +static int falcon_queue_rewind(struct nvgpu_falcon *flcn, struct nvgpu_falcon_queue *queue) { struct gk20a *g = flcn->g; @@ -136,12 +136,12 @@ exit: } /* EMEM-Q specific ops */ -static int flcn_queue_push_emem(struct nvgpu_falcon *flcn, +static int falcon_queue_push_emem(struct nvgpu_falcon *flcn, struct nvgpu_falcon_queue *queue, void *data, u32 size) { int err = 0; - err = nvgpu_flcn_copy_to_emem(flcn, queue->position, data, size, 0); + err = nvgpu_falcon_copy_to_emem(flcn, queue->position, data, size, 0); if (err != 0) { nvgpu_err(flcn->g, "flcn-%d, queue-%d", flcn->flcn_id, queue->id); @@ -155,7 +155,7 @@ exit: return err; } -static int flcn_queue_pop_emem(struct nvgpu_falcon *flcn, +static int falcon_queue_pop_emem(struct nvgpu_falcon *flcn, struct nvgpu_falcon_queue *queue, void *data, u32 size, u32 *bytes_read) { @@ -187,7 +187,7 @@ static int flcn_queue_pop_emem(struct nvgpu_falcon *flcn, size = used; } - err = nvgpu_flcn_copy_from_emem(flcn, q_tail, data, size, 0); + err = nvgpu_falcon_copy_from_emem(flcn, q_tail, data, size, 0); if (err != 0) { nvgpu_err(g, "flcn-%d, queue-%d", flcn->flcn_id, queue->id); @@ -203,24 +203,24 @@ exit: } /* assign EMEM queue type specific ops */ -static void flcn_queue_init_emem_queue(struct nvgpu_falcon *flcn, +static void falcon_queue_init_emem_queue(struct nvgpu_falcon *flcn, struct nvgpu_falcon_queue *queue) { - queue->head = flcn_queue_head; - queue->tail = flcn_queue_tail; - queue->has_room = flcn_queue_has_room; - queue->rewind = flcn_queue_rewind; - queue->push = flcn_queue_push_emem; - queue->pop = flcn_queue_pop_emem; + queue->head = falcon_queue_head; + queue->tail = falcon_queue_tail; + queue->has_room = falcon_queue_has_room; + queue->rewind = falcon_queue_rewind; + queue->push = falcon_queue_push_emem; + queue->pop = falcon_queue_pop_emem; } /* DMEM-Q specific ops */ -static int flcn_queue_push_dmem(struct nvgpu_falcon *flcn, +static int falcon_queue_push_dmem(struct nvgpu_falcon *flcn, struct nvgpu_falcon_queue *queue, void *data, u32 size) { int err = 0; - err = nvgpu_flcn_copy_to_dmem(flcn, queue->position, data, size, 0); + err = nvgpu_falcon_copy_to_dmem(flcn, queue->position, data, size, 0); if (err != 0) { nvgpu_err(flcn->g, "flcn-%d, queue-%d", flcn->flcn_id, queue->id); @@ -234,7 +234,7 @@ exit: return err; } -static int flcn_queue_pop_dmem(struct nvgpu_falcon *flcn, +static int falcon_queue_pop_dmem(struct nvgpu_falcon *flcn, struct nvgpu_falcon_queue *queue, void *data, u32 size, u32 *bytes_read) { @@ -266,7 +266,7 @@ static int flcn_queue_pop_dmem(struct nvgpu_falcon *flcn, size = used; } - err = nvgpu_flcn_copy_from_dmem(flcn, q_tail, data, size, 0); + err = nvgpu_falcon_copy_from_dmem(flcn, q_tail, data, size, 0); if (err != 0) { nvgpu_err(g, "flcn-%d, queue-%d", flcn->flcn_id, queue->id); @@ -282,18 +282,18 @@ exit: } /* assign DMEM queue type specific ops */ -static void flcn_queue_init_dmem_queue(struct nvgpu_falcon *flcn, +static void falcon_queue_init_dmem_queue(struct nvgpu_falcon *flcn, struct nvgpu_falcon_queue *queue) { - queue->head = flcn_queue_head; - queue->tail = flcn_queue_tail; - queue->has_room = flcn_queue_has_room; - queue->push = flcn_queue_push_dmem; - queue->pop = flcn_queue_pop_dmem; - queue->rewind = flcn_queue_rewind; + queue->head = falcon_queue_head; + queue->tail = falcon_queue_tail; + queue->has_room = falcon_queue_has_room; + queue->push = falcon_queue_push_dmem; + queue->pop = falcon_queue_pop_dmem; + queue->rewind = falcon_queue_rewind; } -static int flcn_queue_prepare_write(struct nvgpu_falcon *flcn, +static int falcon_queue_prepare_write(struct nvgpu_falcon *flcn, struct nvgpu_falcon_queue *queue, u32 size) { bool q_rewind = false; @@ -325,7 +325,7 @@ exit: /* queue public functions */ /* queue push operation with lock */ -int nvgpu_flcn_queue_push(struct nvgpu_falcon *flcn, +int nvgpu_falcon_queue_push(struct nvgpu_falcon *flcn, struct nvgpu_falcon_queue *queue, void *data, u32 size) { int err = 0; @@ -340,7 +340,7 @@ int nvgpu_flcn_queue_push(struct nvgpu_falcon *flcn, /* acquire mutex */ nvgpu_mutex_acquire(&queue->mutex); - err = flcn_queue_prepare_write(flcn, queue, size); + err = falcon_queue_prepare_write(flcn, queue, size); if (err != 0) { nvgpu_err(flcn->g, "flcn-%d queue-%d, fail to open", flcn->flcn_id, queue->id); @@ -367,7 +367,7 @@ exit: } /* queue pop operation with lock */ -int nvgpu_flcn_queue_pop(struct nvgpu_falcon *flcn, +int nvgpu_falcon_queue_pop(struct nvgpu_falcon *flcn, struct nvgpu_falcon_queue *queue, void *data, u32 size, u32 *bytes_read) { @@ -409,7 +409,7 @@ exit: return err; } -int nvgpu_flcn_queue_rewind(struct nvgpu_falcon *flcn, +int nvgpu_falcon_queue_rewind(struct nvgpu_falcon *flcn, struct nvgpu_falcon_queue *queue) { int err = 0; @@ -428,7 +428,7 @@ int nvgpu_flcn_queue_rewind(struct nvgpu_falcon *flcn, } /* queue is_empty check with lock */ -bool nvgpu_flcn_queue_is_empty(struct nvgpu_falcon *flcn, +bool nvgpu_falcon_queue_is_empty(struct nvgpu_falcon *flcn, struct nvgpu_falcon_queue *queue) { u32 q_head = 0; @@ -459,7 +459,7 @@ exit: return q_head == q_tail; } -void nvgpu_flcn_queue_free(struct nvgpu_falcon *flcn, +void nvgpu_falcon_queue_free(struct nvgpu_falcon *flcn, struct nvgpu_falcon_queue *queue) { nvgpu_log(flcn->g, gpu_dbg_pmu, "flcn id-%d q-id %d: index %d ", @@ -472,7 +472,7 @@ void nvgpu_flcn_queue_free(struct nvgpu_falcon *flcn, (void) memset(queue, 0, sizeof(struct nvgpu_falcon_queue)); } -int nvgpu_flcn_queue_init(struct nvgpu_falcon *flcn, +int nvgpu_falcon_queue_init(struct nvgpu_falcon *flcn, struct nvgpu_falcon_queue *queue) { struct gk20a *g = flcn->g; @@ -485,10 +485,10 @@ int nvgpu_flcn_queue_init(struct nvgpu_falcon *flcn, switch (queue->queue_type) { case QUEUE_TYPE_DMEM: - flcn_queue_init_dmem_queue(flcn, queue); + falcon_queue_init_dmem_queue(flcn, queue); break; case QUEUE_TYPE_EMEM: - flcn_queue_init_emem_queue(flcn, queue); + falcon_queue_init_emem_queue(flcn, queue); break; default: err = -EINVAL; diff --git a/drivers/gpu/nvgpu/common/fb/fb_gv100.c b/drivers/gpu/nvgpu/common/fb/fb_gv100.c index 61be20969..91ae0850b 100644 --- a/drivers/gpu/nvgpu/common/fb/fb_gv100.c +++ b/drivers/gpu/nvgpu/common/fb/fb_gv100.c @@ -161,7 +161,7 @@ int gv100_fb_memory_unlock(struct gk20a *g) g->ops.mc.enable(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_NVDEC)); /* nvdec falcon reset */ - nvgpu_flcn_reset(&g->nvdec_flcn); + nvgpu_falcon_reset(&g->nvdec_flcn); hsbin_hdr = (struct bin_hdr *)mem_unlock_fw->data; fw_hdr = (struct acr_fw_header *)(mem_unlock_fw->data + @@ -184,10 +184,10 @@ int gv100_fb_memory_unlock(struct gk20a *g) } /* Clear interrupts */ - nvgpu_flcn_set_irq(&g->nvdec_flcn, false, 0x0, 0x0); + nvgpu_falcon_set_irq(&g->nvdec_flcn, false, 0x0, 0x0); /* Copy Non Secure IMEM code */ - nvgpu_flcn_copy_to_imem(&g->nvdec_flcn, 0, + nvgpu_falcon_copy_to_imem(&g->nvdec_flcn, 0, (u8 *)&mem_unlock_ucode[ mem_unlock_ucode_header[OS_CODE_OFFSET] >> 2], mem_unlock_ucode_header[OS_CODE_SIZE], 0, false, @@ -196,33 +196,33 @@ int gv100_fb_memory_unlock(struct gk20a *g) /* Put secure code after non-secure block */ sec_imem_dest = GET_NEXT_BLOCK(mem_unlock_ucode_header[OS_CODE_SIZE]); - nvgpu_flcn_copy_to_imem(&g->nvdec_flcn, sec_imem_dest, + nvgpu_falcon_copy_to_imem(&g->nvdec_flcn, sec_imem_dest, (u8 *)&mem_unlock_ucode[ mem_unlock_ucode_header[APP_0_CODE_OFFSET] >> 2], mem_unlock_ucode_header[APP_0_CODE_SIZE], 0, true, GET_IMEM_TAG(mem_unlock_ucode_header[APP_0_CODE_OFFSET])); /* load DMEM: ensure that signatures are patched */ - nvgpu_flcn_copy_to_dmem(&g->nvdec_flcn, 0, (u8 *)&mem_unlock_ucode[ + nvgpu_falcon_copy_to_dmem(&g->nvdec_flcn, 0, (u8 *)&mem_unlock_ucode[ mem_unlock_ucode_header[OS_DATA_OFFSET] >> 2], mem_unlock_ucode_header[OS_DATA_SIZE], 0); /* Write non-zero value to mailbox register which is updated by * mem_unlock bin to denote its return status. */ - nvgpu_flcn_mailbox_write(&g->nvdec_flcn, 0, 0xdeadbeef); + nvgpu_falcon_mailbox_write(&g->nvdec_flcn, 0, 0xdeadbeef); /* set BOOTVEC to start of non-secure code */ - nvgpu_flcn_bootstrap(&g->nvdec_flcn, 0); + nvgpu_falcon_bootstrap(&g->nvdec_flcn, 0); /* wait for complete & halt */ - nvgpu_flcn_wait_for_halt(&g->nvdec_flcn, MEM_UNLOCK_TIMEOUT); + nvgpu_falcon_wait_for_halt(&g->nvdec_flcn, MEM_UNLOCK_TIMEOUT); /* check mem unlock status */ - val = nvgpu_flcn_mailbox_read(&g->nvdec_flcn, 0); + val = nvgpu_falcon_mailbox_read(&g->nvdec_flcn, 0); if (val != 0U) { nvgpu_err(g, "memory unlock failed, err %x", val); - nvgpu_flcn_dump_stats(&g->nvdec_flcn); + nvgpu_falcon_dump_stats(&g->nvdec_flcn); err = -1; goto exit; } diff --git a/drivers/gpu/nvgpu/common/pmu/acr_gm20b.c b/drivers/gpu/nvgpu/common/pmu/acr_gm20b.c index bea458431..a92beb32d 100644 --- a/drivers/gpu/nvgpu/common/pmu/acr_gm20b.c +++ b/drivers/gpu/nvgpu/common/pmu/acr_gm20b.c @@ -1059,16 +1059,16 @@ static int nvgpu_gm20b_acr_wait_for_completion(struct gk20a *g, nvgpu_log_fn(g, " "); - completion = nvgpu_flcn_wait_for_halt(flcn, timeout); + completion = nvgpu_falcon_wait_for_halt(flcn, timeout); if (completion != 0U) { nvgpu_err(g, "flcn-%d: ACR boot timed out", flcn->flcn_id); goto exit; } nvgpu_pmu_dbg(g, "flcn-%d: ACR capabilities %x\n", flcn->flcn_id, - nvgpu_flcn_mailbox_read(flcn, FALCON_MAILBOX_1)); + nvgpu_falcon_mailbox_read(flcn, FALCON_MAILBOX_1)); - data = nvgpu_flcn_mailbox_read(flcn, FALCON_MAILBOX_0); + data = nvgpu_falcon_mailbox_read(flcn, FALCON_MAILBOX_0); if (data != 0U) { nvgpu_err(g, "flcn-%d: ACR boot failed, err %x", flcn->flcn_id, data); diff --git a/drivers/gpu/nvgpu/common/pmu/pmu.c b/drivers/gpu/nvgpu/common/pmu/pmu.c index dc081448d..88dff3328 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu.c @@ -55,7 +55,7 @@ static int pmu_enable_hw(struct nvgpu_pmu *pmu, bool enable) g->blcg_enabled); } - if (nvgpu_flcn_mem_scrub_wait(pmu->flcn) != 0) { + if (nvgpu_falcon_mem_scrub_wait(pmu->flcn) != 0) { /* keep PMU falcon/engine in reset * if IMEM/DMEM scrubbing fails */ @@ -90,7 +90,7 @@ static int pmu_enable(struct nvgpu_pmu *pmu, bool enable) goto exit; } - err = nvgpu_flcn_wait_idle(pmu->flcn); + err = nvgpu_falcon_wait_idle(pmu->flcn); if (err != 0) { goto exit; } @@ -110,7 +110,7 @@ int nvgpu_pmu_reset(struct gk20a *g) nvgpu_log_fn(g, " %s ", g->name); - err = nvgpu_flcn_wait_idle(pmu->flcn); + err = nvgpu_falcon_wait_idle(pmu->flcn); if (err != 0) { goto exit; } @@ -308,7 +308,7 @@ int nvgpu_init_pmu_support(struct gk20a *g) if (nvgpu_is_enabled(g, NVGPU_SUPPORT_SEC2_RTOS)) { /* Reset PMU engine */ - err = nvgpu_flcn_reset(&g->pmu_flcn); + err = nvgpu_falcon_reset(&g->pmu_flcn); /* Bootstrap PMU from SEC2 RTOS*/ err = nvgpu_sec2_bootstrap_ls_falcons(g, &g->sec2, @@ -322,7 +322,7 @@ int nvgpu_init_pmu_support(struct gk20a *g) * clear halt interrupt to avoid PMU-RTOS ucode * hitting breakpoint due to PMU halt */ - err = nvgpu_flcn_clear_halt_intr_status(&g->pmu_flcn, + err = nvgpu_falcon_clear_halt_intr_status(&g->pmu_flcn, gk20a_get_gr_idle_timeout(g)); if (err != 0) { goto exit; @@ -377,14 +377,14 @@ int nvgpu_pmu_process_init_msg(struct nvgpu_pmu *pmu, g->ops.pmu.pmu_msgq_tail(pmu, &tail, QUEUE_GET); - nvgpu_flcn_copy_from_dmem(pmu->flcn, tail, + nvgpu_falcon_copy_from_dmem(pmu->flcn, tail, (u8 *)&msg->hdr, PMU_MSG_HDR_SIZE, 0); if (msg->hdr.unit_id != PMU_UNIT_INIT) { nvgpu_err(g, "expecting init msg"); return -EINVAL; } - nvgpu_flcn_copy_from_dmem(pmu->flcn, tail + PMU_MSG_HDR_SIZE, + nvgpu_falcon_copy_from_dmem(pmu->flcn, tail + PMU_MSG_HDR_SIZE, (u8 *)&msg->msg, msg->hdr.size - PMU_MSG_HDR_SIZE, 0); if (msg->msg.init.msg_type != PMU_INIT_MSG_TYPE_PMU_INIT) { @@ -399,7 +399,7 @@ int nvgpu_pmu_process_init_msg(struct nvgpu_pmu *pmu, if (!pmu->gid_info.valid) { u32 *gid_hdr_data = (u32 *)(gid_data.signature); - nvgpu_flcn_copy_from_dmem(pmu->flcn, + nvgpu_falcon_copy_from_dmem(pmu->flcn, pv->get_pmu_init_msg_pmu_sw_mg_off(init), (u8 *)&gid_data, sizeof(struct pmu_sha1_gid_data), 0); @@ -585,7 +585,7 @@ int nvgpu_pmu_destroy(struct gk20a *g) nvgpu_mutex_release(&pmu->isr_mutex); for (i = 0U; i < PMU_QUEUE_COUNT; i++) { - nvgpu_flcn_queue_free(pmu->flcn, &pmu->queue[i]); + nvgpu_falcon_queue_free(pmu->flcn, &pmu->queue[i]); } nvgpu_pmu_state_change(g, PMU_STATE_OFF, false); diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_debug.c b/drivers/gpu/nvgpu/common/pmu/pmu_debug.c index 085dc135a..256c5e6ec 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_debug.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_debug.c @@ -34,7 +34,7 @@ void nvgpu_pmu_dump_elpg_stats(struct nvgpu_pmu *pmu) /* Print PG stats */ nvgpu_err(g, "Print PG stats"); - nvgpu_flcn_print_dmem(pmu->flcn, + nvgpu_falcon_print_dmem(pmu->flcn, pmu->stat_dmem_offset[PMU_PG_ELPG_ENGINE_ID_GRAPHICS], sizeof(struct pmu_pg_stats_v2)); @@ -45,7 +45,7 @@ void nvgpu_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu) { struct gk20a *g = pmu->g; - nvgpu_flcn_dump_stats(pmu->flcn); + nvgpu_falcon_dump_stats(pmu->flcn); g->ops.pmu.pmu_dump_falcon_stats(pmu); nvgpu_err(g, "pmu state: %d", pmu->pmu_state); diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.c b/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.c index 0d5a62ca0..3108a5690 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.c @@ -158,7 +158,7 @@ void gk20a_pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable) g->ops.mc.intr_unit_config(g, MC_INTR_UNIT_DISABLE, false, mc_intr_mask_1_pmu_enabled_f()); - nvgpu_flcn_set_irq(pmu->flcn, false, 0x0, 0x0); + nvgpu_falcon_set_irq(pmu->flcn, false, 0x0, 0x0); if (enable) { intr_dest = g->ops.pmu.get_irqdest(g); @@ -172,7 +172,7 @@ void gk20a_pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable) pwr_falcon_irqmset_swgen0_f(1) | pwr_falcon_irqmset_swgen1_f(1); - nvgpu_flcn_set_irq(pmu->flcn, true, intr_mask, intr_dest); + nvgpu_falcon_set_irq(pmu->flcn, true, intr_mask, intr_dest); g->ops.mc.intr_unit_config(g, MC_INTR_UNIT_ENABLE, true, mc_intr_mask_0_pmu_enabled_f()); @@ -217,7 +217,7 @@ int pmu_bootstrap(struct nvgpu_pmu *pmu) << GK20A_PMU_DMEM_BLKSIZE2) - g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu); - nvgpu_flcn_copy_to_dmem(pmu->flcn, addr_args, + nvgpu_falcon_copy_to_dmem(pmu->flcn, addr_args, (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); @@ -263,7 +263,7 @@ int pmu_bootstrap(struct nvgpu_pmu *pmu) pwr_falcon_dmatrfcmd_ctxdma_f(GK20A_PMU_DMAIDX_UCODE)); } - nvgpu_flcn_bootstrap(g->pmu.flcn, desc->bootloader_entry_point); + nvgpu_falcon_bootstrap(g->pmu.flcn, desc->bootloader_entry_point); gk20a_writel(g, pwr_falcon_os_r(), desc->app_version); @@ -743,7 +743,7 @@ void gk20a_pmu_isr(struct gk20a *g) if (recheck) { queue = &pmu->queue[PMU_MESSAGE_QUEUE]; - if (!nvgpu_flcn_queue_is_empty(pmu->flcn, queue)) { + if (!nvgpu_falcon_queue_is_empty(pmu->flcn, queue)) { gk20a_writel(g, pwr_falcon_irqsset_r(), pwr_falcon_irqsset_swgen0_set_f()); } @@ -819,7 +819,7 @@ void gk20a_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, struct nvgpu_pmu *pmu = &g->pmu; struct pmu_pg_stats stats; - nvgpu_flcn_copy_from_dmem(pmu->flcn, + nvgpu_falcon_copy_from_dmem(pmu->flcn, pmu->stat_dmem_offset[pg_engine_id], (u8 *)&stats, sizeof(struct pmu_pg_stats), 0); diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_gm20b.c b/drivers/gpu/nvgpu/common/pmu/pmu_gm20b.c index 9fb53286c..2df18f40d 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_gm20b.c @@ -285,7 +285,7 @@ int gm20b_ns_pmu_setup_hw_and_bootstrap(struct gk20a *g) nvgpu_log_fn(g, " "); nvgpu_mutex_acquire(&pmu->isr_mutex); - nvgpu_flcn_reset(pmu->flcn); + nvgpu_falcon_reset(pmu->flcn); pmu->isr_enabled = true; nvgpu_mutex_release(&pmu->isr_mutex); @@ -340,7 +340,7 @@ void gm20b_update_lspmu_cmdline_args(struct gk20a *g) g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu); g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx( pmu, GK20A_PMU_DMAIDX_VIRT); - nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args, + nvgpu_falcon_copy_to_dmem(pmu->flcn, g->acr.pmu_args, (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); } @@ -363,7 +363,7 @@ static int gm20b_bl_bootstrap(struct gk20a *g, pwr_pmu_new_instblk_target_sys_coh_f() : pwr_pmu_new_instblk_target_sys_ncoh_f())) ; - nvgpu_flcn_bl_bootstrap(&g->pmu_flcn, bl_info); + nvgpu_falcon_bl_bootstrap(&g->pmu_flcn, bl_info); return 0; } @@ -384,7 +384,7 @@ int gm20b_pmu_setup_hw_and_bl_bootstrap(struct gk20a *g, */ g->ops.pmu.pmu_enable_irq(pmu, false); pmu->isr_enabled = false; - err = nvgpu_flcn_reset(acr_desc->acr_flcn); + err = nvgpu_falcon_reset(acr_desc->acr_flcn); if (err != 0) { nvgpu_mutex_release(&pmu->isr_mutex); goto exit; diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_gp106.c b/drivers/gpu/nvgpu/common/pmu/pmu_gp106.c index 61af7e429..ddb294bf1 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_gp106.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_gp106.c @@ -169,7 +169,7 @@ void gp106_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, struct nvgpu_pmu *pmu = &g->pmu; struct pmu_pg_stats_v2 stats; - nvgpu_flcn_copy_from_dmem(pmu->flcn, + nvgpu_falcon_copy_from_dmem(pmu->flcn, pmu->stat_dmem_offset[pg_engine_id], (u8 *)&stats, sizeof(struct pmu_pg_stats_v2), 0); @@ -322,7 +322,7 @@ void gp106_update_lspmu_cmdline_args(struct gk20a *g) g->ops.pmu_ver.config_pmu_cmdline_args_super_surface(pmu); } - nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args, + nvgpu_falcon_copy_to_dmem(pmu->flcn, g->acr.pmu_args, (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_gp10b.c b/drivers/gpu/nvgpu/common/pmu/pmu_gp10b.c index 76ad5d487..55a2eb16f 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_gp10b.c @@ -263,7 +263,7 @@ void gp10b_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, struct nvgpu_pmu *pmu = &g->pmu; struct pmu_pg_stats_v1 stats; - nvgpu_flcn_copy_from_dmem(pmu->flcn, + nvgpu_falcon_copy_from_dmem(pmu->flcn, pmu->stat_dmem_offset[pg_engine_id], (u8 *)&stats, sizeof(struct pmu_pg_stats_v1), 0); diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_gv11b.c b/drivers/gpu/nvgpu/common/pmu/pmu_gv11b.c index be7b238c1..aa6ac9c6f 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_gv11b.c @@ -216,7 +216,7 @@ int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu) << GK20A_PMU_DMEM_BLKSIZE2) - g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu); - nvgpu_flcn_copy_to_dmem(pmu->flcn, addr_args, + nvgpu_falcon_copy_to_dmem(pmu->flcn, addr_args, (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); @@ -281,7 +281,7 @@ int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu) pwr_falcon_dmatrfcmd_ctxdma_f(GK20A_PMU_DMAIDX_UCODE)); } - nvgpu_flcn_bootstrap(pmu->flcn, desc->bootloader_entry_point); + nvgpu_falcon_bootstrap(pmu->flcn, desc->bootloader_entry_point); gk20a_writel(g, pwr_falcon_os_r(), desc->app_version); diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c index 53e42a316..79211537b 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c @@ -138,7 +138,7 @@ int nvgpu_pmu_queue_init(struct nvgpu_pmu *pmu, queue->queue_type = QUEUE_TYPE_DMEM; g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params(queue, id, init); - err = nvgpu_flcn_queue_init(pmu->flcn, queue); + err = nvgpu_falcon_queue_init(pmu->flcn, queue); if (err != 0) { nvgpu_err(g, "queue-%d init failed", queue->id); } @@ -243,7 +243,7 @@ static int pmu_write_cmd(struct nvgpu_pmu *pmu, struct pmu_cmd *cmd, nvgpu_timeout_init(g, &timeout, timeout_ms, NVGPU_TIMER_CPU_TIMER); do { - err = nvgpu_flcn_queue_push(pmu->flcn, queue, cmd, cmd->hdr.size); + err = nvgpu_falcon_queue_push(pmu->flcn, queue, cmd, cmd->hdr.size); if (err == -EAGAIN && nvgpu_timeout_expired(&timeout) == 0) { nvgpu_usleep_range(1000, 2000); } else { @@ -279,7 +279,7 @@ static int pmu_cmd_payload_extract_rpc(struct gk20a *g, struct pmu_cmd *cmd, goto clean_up; } - nvgpu_flcn_copy_to_dmem(pmu->flcn, dmem_alloc_offset, + nvgpu_falcon_copy_to_dmem(pmu->flcn, dmem_alloc_offset, payload->rpc.prpc, payload->rpc.size_rpc, 0); cmd->cmd.rpc.rpc_dmem_size = payload->rpc.size_rpc; @@ -354,7 +354,7 @@ static int pmu_cmd_payload_extract(struct gk20a *g, struct pmu_cmd *cmd, payload->in.buf, payload->in.fb_size); } else { - nvgpu_flcn_copy_to_dmem(pmu->flcn, + nvgpu_falcon_copy_to_dmem(pmu->flcn, (pv->pmu_allocation_get_dmem_offset(pmu, in)), payload->in.buf, payload->in.size, 0); } @@ -537,7 +537,7 @@ static int pmu_response_handle(struct nvgpu_pmu *pmu, } if (pv->pmu_allocation_get_dmem_size(pmu, pv->get_pmu_seq_out_a_ptr(seq)) != 0U) { - nvgpu_flcn_copy_from_dmem(pmu->flcn, + nvgpu_falcon_copy_from_dmem(pmu->flcn, pv->pmu_allocation_get_dmem_offset(pmu, pv->get_pmu_seq_out_a_ptr(seq)), seq->out_payload, @@ -637,11 +637,11 @@ static bool pmu_read_message(struct nvgpu_pmu *pmu, *status = 0; - if (nvgpu_flcn_queue_is_empty(pmu->flcn, queue)) { + if (nvgpu_falcon_queue_is_empty(pmu->flcn, queue)) { return false; } - err = nvgpu_flcn_queue_pop(pmu->flcn, queue, &msg->hdr, + err = nvgpu_falcon_queue_pop(pmu->flcn, queue, &msg->hdr, PMU_MSG_HDR_SIZE, &bytes_read); if (err != 0 || bytes_read != PMU_MSG_HDR_SIZE) { nvgpu_err(g, "fail to read msg from queue %d", queue->id); @@ -650,14 +650,14 @@ static bool pmu_read_message(struct nvgpu_pmu *pmu, } if (msg->hdr.unit_id == PMU_UNIT_REWIND) { - err = nvgpu_flcn_queue_rewind(pmu->flcn, queue); + err = nvgpu_falcon_queue_rewind(pmu->flcn, queue); if (err != 0) { nvgpu_err(g, "fail to rewind queue %d", queue->id); *status = err | -EINVAL; goto clean_up; } /* read again after rewind */ - err = nvgpu_flcn_queue_pop(pmu->flcn, queue, &msg->hdr, + err = nvgpu_falcon_queue_pop(pmu->flcn, queue, &msg->hdr, PMU_MSG_HDR_SIZE, &bytes_read); if (err != 0 || bytes_read != PMU_MSG_HDR_SIZE) { nvgpu_err(g, @@ -676,7 +676,7 @@ static bool pmu_read_message(struct nvgpu_pmu *pmu, if (msg->hdr.size > PMU_MSG_HDR_SIZE) { read_size = msg->hdr.size - PMU_MSG_HDR_SIZE; - err = nvgpu_flcn_queue_pop(pmu->flcn, queue, &msg->msg, + err = nvgpu_falcon_queue_pop(pmu->flcn, queue, &msg->msg, read_size, &bytes_read); if (err != 0 || bytes_read != read_size) { nvgpu_err(g, diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c index 007ccc22b..e7f604d69 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c @@ -226,7 +226,7 @@ int nvgpu_pmu_load_update(struct gk20a *g) nvgpu_pmu_perfmon_get_samples_rpc(pmu); load = pmu->load; } else { - nvgpu_flcn_copy_from_dmem(pmu->flcn, pmu->sample_buffer, + nvgpu_falcon_copy_from_dmem(pmu->flcn, pmu->sample_buffer, (u8 *)&load, 2 * 1, 0); } diff --git a/drivers/gpu/nvgpu/common/sec2/sec2.c b/drivers/gpu/nvgpu/common/sec2/sec2.c index 4b3c38fde..ea93106bf 100644 --- a/drivers/gpu/nvgpu/common/sec2/sec2.c +++ b/drivers/gpu/nvgpu/common/sec2/sec2.c @@ -69,7 +69,7 @@ int nvgpu_sec2_queue_init(struct nvgpu_sec2 *sec2, u32 id, queue->oflag = oflag; queue->queue_type = QUEUE_TYPE_EMEM; - err = nvgpu_flcn_queue_init(sec2->flcn, queue); + err = nvgpu_falcon_queue_init(sec2->flcn, queue); if (err != 0) { nvgpu_err(g, "queue-%d init failed", queue->id); } @@ -180,7 +180,7 @@ int nvgpu_sec2_destroy(struct gk20a *g) nvgpu_mutex_release(&sec2->isr_mutex); for (i = 0; i < SEC2_QUEUE_NUM; i++) { - nvgpu_flcn_queue_free(sec2->flcn, &sec2->queue[i]); + nvgpu_falcon_queue_free(sec2->flcn, &sec2->queue[i]); } sec2->sec2_ready = false; diff --git a/drivers/gpu/nvgpu/common/sec2/sec2_ipc.c b/drivers/gpu/nvgpu/common/sec2/sec2_ipc.c index 8c83cbc5d..f401a9cdb 100644 --- a/drivers/gpu/nvgpu/common/sec2/sec2_ipc.c +++ b/drivers/gpu/nvgpu/common/sec2/sec2_ipc.c @@ -125,7 +125,7 @@ static int sec2_write_cmd(struct nvgpu_sec2 *sec2, nvgpu_timeout_init(g, &timeout, timeout_ms, NVGPU_TIMER_CPU_TIMER); do { - err = nvgpu_flcn_queue_push(&g->sec2_flcn, queue, cmd, + err = nvgpu_falcon_queue_push(&g->sec2_flcn, queue, cmd, cmd->hdr.size); if ((err == -EAGAIN) && (nvgpu_timeout_expired(&timeout) == 0)) { nvgpu_usleep_range(1000U, 2000U); @@ -249,11 +249,11 @@ static bool sec2_read_message(struct nvgpu_sec2 *sec2, *status = 0U; - if (nvgpu_flcn_queue_is_empty(sec2->flcn, queue)) { + if (nvgpu_falcon_queue_is_empty(sec2->flcn, queue)) { return false; } - err = nvgpu_flcn_queue_pop(sec2->flcn, queue, &msg->hdr, + err = nvgpu_falcon_queue_pop(sec2->flcn, queue, &msg->hdr, PMU_MSG_HDR_SIZE, &bytes_read); if ((err != 0) || (bytes_read != PMU_MSG_HDR_SIZE)) { nvgpu_err(g, "fail to read msg from queue %d", queue->id); @@ -262,7 +262,7 @@ static bool sec2_read_message(struct nvgpu_sec2 *sec2, } if (msg->hdr.unit_id == NV_SEC2_UNIT_REWIND) { - err = nvgpu_flcn_queue_rewind(sec2->flcn, queue); + err = nvgpu_falcon_queue_rewind(sec2->flcn, queue); if (err != 0) { nvgpu_err(g, "fail to rewind queue %d", queue->id); *status = err | -EINVAL; @@ -270,7 +270,7 @@ static bool sec2_read_message(struct nvgpu_sec2 *sec2, } /* read again after rewind */ - err = nvgpu_flcn_queue_pop(sec2->flcn, queue, &msg->hdr, + err = nvgpu_falcon_queue_pop(sec2->flcn, queue, &msg->hdr, PMU_MSG_HDR_SIZE, &bytes_read); if ((err != 0) || (bytes_read != PMU_MSG_HDR_SIZE)) { nvgpu_err(g, @@ -289,7 +289,7 @@ static bool sec2_read_message(struct nvgpu_sec2 *sec2, if (msg->hdr.size > PMU_MSG_HDR_SIZE) { read_size = msg->hdr.size - PMU_MSG_HDR_SIZE; - err = nvgpu_flcn_queue_pop(sec2->flcn, queue, &msg->msg, + err = nvgpu_falcon_queue_pop(sec2->flcn, queue, &msg->msg, read_size, &bytes_read); if ((err != 0) || (bytes_read != read_size)) { nvgpu_err(g, @@ -315,7 +315,7 @@ static int sec2_process_init_msg(struct nvgpu_sec2 *sec2, g->ops.sec2.msgq_tail(g, sec2, &tail, QUEUE_GET); - err = nvgpu_flcn_copy_from_emem(sec2->flcn, tail, + err = nvgpu_falcon_copy_from_emem(sec2->flcn, tail, (u8 *)&msg->hdr, PMU_MSG_HDR_SIZE, 0U); if (err != 0) { goto exit; @@ -327,7 +327,7 @@ static int sec2_process_init_msg(struct nvgpu_sec2 *sec2, goto exit; } - err = nvgpu_flcn_copy_from_emem(sec2->flcn, tail + PMU_MSG_HDR_SIZE, + err = nvgpu_falcon_copy_from_emem(sec2->flcn, tail + PMU_MSG_HDR_SIZE, (u8 *)&msg->msg, msg->hdr.size - PMU_MSG_HDR_SIZE, 0U); if (err != 0) { goto exit; diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index cb513cfa7..c000b8fb7 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -122,7 +122,7 @@ void gk20a_fecs_dump_falcon_stats(struct gk20a *g) { unsigned int i; - nvgpu_flcn_dump_stats(&g->fecs_flcn); + nvgpu_falcon_dump_stats(&g->fecs_flcn); for (i = 0; i < g->ops.gr.fecs_ctxsw_mailbox_size(); i++) { nvgpu_err(g, "gr_fecs_ctxsw_mailbox_r(%d) : 0x%x", diff --git a/drivers/gpu/nvgpu/gp106/bios_gp106.c b/drivers/gpu/nvgpu/gp106/bios_gp106.c index 82b365bc8..777eabe3d 100644 --- a/drivers/gpu/nvgpu/gp106/bios_gp106.c +++ b/drivers/gpu/nvgpu/gp106/bios_gp106.c @@ -46,7 +46,7 @@ static void upload_code(struct gk20a *g, u32 dst, u8 *src, u32 size, u8 port, bool sec) { - nvgpu_flcn_copy_to_imem(g->pmu.flcn, dst, src, size, port, sec, + nvgpu_falcon_copy_to_imem(g->pmu.flcn, dst, src, size, port, sec, dst >> 8); } @@ -82,7 +82,7 @@ int gp106_bios_devinit(struct gk20a *g) nvgpu_log_fn(g, " "); - if (nvgpu_flcn_reset(g->pmu.flcn) != 0) { + if (nvgpu_falcon_reset(g->pmu.flcn) != 0) { err = -ETIMEDOUT; goto out; } @@ -108,7 +108,7 @@ int gp106_bios_devinit(struct gk20a *g) g->bios.bootscripts_size, 0); - nvgpu_flcn_bootstrap(g->pmu.flcn, g->bios.devinit.code_entry_point); + nvgpu_falcon_bootstrap(g->pmu.flcn, g->bios.devinit.code_entry_point); nvgpu_timeout_init(g, &timeout, PMU_BOOT_TIMEOUT_MAX / @@ -126,7 +126,7 @@ int gp106_bios_devinit(struct gk20a *g) err = -ETIMEDOUT; } - nvgpu_flcn_clear_halt_intr_status(g->pmu.flcn, + nvgpu_falcon_clear_halt_intr_status(g->pmu.flcn, gk20a_get_gr_idle_timeout(g)); out: @@ -138,7 +138,7 @@ int gp106_bios_preos_wait_for_halt(struct gk20a *g) { int err = 0; - if (nvgpu_flcn_wait_for_halt(g->pmu.flcn, + if (nvgpu_falcon_wait_for_halt(g->pmu.flcn, PMU_BOOT_TIMEOUT_MAX / 1000) != 0) { err = -ETIMEDOUT; } @@ -152,7 +152,7 @@ int gp106_bios_preos(struct gk20a *g) nvgpu_log_fn(g, " "); - if (nvgpu_flcn_reset(g->pmu.flcn) != 0) { + if (nvgpu_falcon_reset(g->pmu.flcn) != 0) { err = -ETIMEDOUT; goto out; } @@ -174,11 +174,11 @@ int gp106_bios_preos(struct gk20a *g) g->bios.preos.dmem_size, 0); - nvgpu_flcn_bootstrap(g->pmu.flcn, g->bios.preos.code_entry_point); + nvgpu_falcon_bootstrap(g->pmu.flcn, g->bios.preos.code_entry_point); err = g->ops.bios.preos_wait_for_halt(g); - nvgpu_flcn_clear_halt_intr_status(g->pmu.flcn, + nvgpu_falcon_clear_halt_intr_status(g->pmu.flcn, gk20a_get_gr_idle_timeout(g)); out: diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c index 37c9d4acc..85edab64e 100644 --- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c +++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c @@ -77,7 +77,7 @@ static int sec2_flcn_bl_bootstrap(struct gk20a *g, data |= (1U << 3U); gk20a_writel(g, psec_falcon_engctl_r(), data); - err = nvgpu_flcn_bl_bootstrap(&g->sec2_flcn, bl_info); + err = nvgpu_falcon_bl_bootstrap(&g->sec2_flcn, bl_info); return err; } @@ -90,7 +90,7 @@ int gp106_sec2_setup_hw_and_bl_bootstrap(struct gk20a *g, nvgpu_log_fn(g, " "); - nvgpu_flcn_reset(&g->sec2_flcn); + nvgpu_falcon_reset(&g->sec2_flcn); data = gk20a_readl(g, psec_fbif_ctl_r()); data |= psec_fbif_ctl_allow_phys_no_ctx_allow_f(); diff --git a/drivers/gpu/nvgpu/gv100/gsp_gv100.c b/drivers/gpu/nvgpu/gv100/gsp_gv100.c index 2219d6cbe..848e80166 100644 --- a/drivers/gpu/nvgpu/gv100/gsp_gv100.c +++ b/drivers/gpu/nvgpu/gv100/gsp_gv100.c @@ -68,7 +68,7 @@ static int gsp_flcn_bl_bootstrap(struct gk20a *g, data |= pgsp_falcon_engctl_switch_context_true_f(); gk20a_writel(g, pgsp_falcon_engctl_r(), data); - status = nvgpu_flcn_bl_bootstrap(&g->gsp_flcn, bl_info); + status = nvgpu_falcon_bl_bootstrap(&g->gsp_flcn, bl_info); return status; } @@ -80,7 +80,7 @@ int gv100_gsp_setup_hw_and_bl_bootstrap(struct gk20a *g, u32 data = 0; int err = 0; - err = nvgpu_flcn_reset(&g->gsp_flcn); + err = nvgpu_falcon_reset(&g->gsp_flcn); if (err != 0) { goto exit; } diff --git a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c index d259d97a9..ec8a23cea 100644 --- a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c +++ b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c @@ -470,7 +470,7 @@ static u32 gv100_nvlink_minion_load(struct gk20a *g) } /* nvdec falcon reset */ - nvgpu_flcn_reset(&g->minion_flcn); + nvgpu_falcon_reset(&g->minion_flcn); /* Read ucode header */ minion_hdr->os_code_offset = minion_extract_word(nvgpu_minion_fw, @@ -593,17 +593,17 @@ static u32 gv100_nvlink_minion_load(struct gk20a *g) " - Ucode Data Size = %u", minion_hdr->ucode_data_size); /* Clear interrupts */ - nvgpu_flcn_set_irq(&g->minion_flcn, true, MINION_FALCON_INTR_MASK, + nvgpu_falcon_set_irq(&g->minion_flcn, true, MINION_FALCON_INTR_MASK, MINION_FALCON_INTR_DEST); /* Copy Non Secure IMEM code */ - nvgpu_flcn_copy_to_imem(&g->minion_flcn, 0, + nvgpu_falcon_copy_to_imem(&g->minion_flcn, 0, (u8 *)&ndev->minion_img[minion_hdr->os_code_offset], minion_hdr->os_code_size, 0, false, GET_IMEM_TAG(minion_hdr->os_code_offset)); /* Copy Non Secure DMEM code */ - nvgpu_flcn_copy_to_dmem(&g->minion_flcn, 0, + nvgpu_falcon_copy_to_dmem(&g->minion_flcn, 0, (u8 *)&ndev->minion_img[minion_hdr->os_data_offset], minion_hdr->os_data_size, 0); @@ -615,21 +615,21 @@ static u32 gv100_nvlink_minion_load(struct gk20a *g) u32 app_data_size = minion_hdr->app_data_sizes[app]; if (app_code_size) - nvgpu_flcn_copy_to_imem(&g->minion_flcn, + nvgpu_falcon_copy_to_imem(&g->minion_flcn, app_code_start, (u8 *)&ndev->minion_img[app_code_start], app_code_size, 0, true, GET_IMEM_TAG(app_code_start)); if (app_data_size) - nvgpu_flcn_copy_to_dmem(&g->minion_flcn, + nvgpu_falcon_copy_to_dmem(&g->minion_flcn, app_data_start, (u8 *)&ndev->minion_img[app_data_start], app_data_size, 0); } /* set BOOTVEC to start of non-secure code */ - nvgpu_flcn_bootstrap(&g->minion_flcn, 0x0); + nvgpu_falcon_bootstrap(&g->minion_flcn, 0x0); nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), NVGPU_TIMER_CPU_TIMER); @@ -2709,7 +2709,7 @@ int gv100_nvlink_early_init(struct gk20a *g) goto nvlink_init_exit; } - err = nvgpu_flcn_sw_init(g, FALCON_ID_MINION); + err = nvgpu_falcon_sw_init(g, FALCON_ID_MINION); if (err != 0) { nvgpu_err(g, "failed to sw init FALCON_ID_MINION"); goto nvlink_init_exit; diff --git a/drivers/gpu/nvgpu/include/nvgpu/falcon.h b/drivers/gpu/nvgpu/include/nvgpu/falcon.h index 770c93ee7..b1a238a32 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/falcon.h +++ b/drivers/gpu/nvgpu/include/nvgpu/falcon.h @@ -95,7 +95,7 @@ /* * Falcon HWCFG request read types defines */ -enum flcn_hwcfg_read { +enum falcon_hwcfg_read { FALCON_IMEM_SIZE = 0, FALCON_DMEM_SIZE, FALCON_CORE_REV, @@ -106,7 +106,7 @@ enum flcn_hwcfg_read { /* * Falcon HWCFG request write types defines */ -enum flcn_hwcfg_write { +enum falcon_hwcfg_write { FALCON_STARTCPU = 0, FALCON_STARTCPU_SECURE, FALCON_BOOTVEC, @@ -116,12 +116,12 @@ enum flcn_hwcfg_write { #define FALCON_MEM_SCRUBBING_TIMEOUT_MAX 1000U #define FALCON_MEM_SCRUBBING_TIMEOUT_DEFAULT 10U -enum flcn_dma_dir { +enum falcon_dma_dir { DMA_TO_FB = 0, DMA_FROM_FB }; -enum flcn_mem_type { +enum falcon_mem_type { MEM_DMEM = 0, MEM_IMEM }; @@ -158,9 +158,9 @@ struct nvgpu_falcon_dma_info { u32 fb_off; u32 flcn_mem_off; u32 size_in_bytes; - enum flcn_dma_dir dir; + enum falcon_dma_dir dir; u32 ctx_dma; - enum flcn_mem_type flcn_mem; + enum falcon_mem_type flcn_mem; u32 is_wait_complete; }; @@ -280,56 +280,56 @@ struct nvgpu_falcon { struct nvgpu_falcon_engine_dependency_ops flcn_engine_dep_ops; }; -int nvgpu_flcn_wait_idle(struct nvgpu_falcon *flcn); -int nvgpu_flcn_wait_for_halt(struct nvgpu_falcon *flcn, unsigned int timeout); -int nvgpu_flcn_clear_halt_intr_status(struct nvgpu_falcon *flcn, +int nvgpu_falcon_wait_idle(struct nvgpu_falcon *flcn); +int nvgpu_falcon_wait_for_halt(struct nvgpu_falcon *flcn, unsigned int timeout); +int nvgpu_falcon_clear_halt_intr_status(struct nvgpu_falcon *flcn, unsigned int timeout); -int nvgpu_flcn_reset(struct nvgpu_falcon *flcn); -void nvgpu_flcn_set_irq(struct nvgpu_falcon *flcn, bool enable, +int nvgpu_falcon_reset(struct nvgpu_falcon *flcn); +void nvgpu_falcon_set_irq(struct nvgpu_falcon *flcn, bool enable, u32 intr_mask, u32 intr_dest); -bool nvgpu_flcn_get_mem_scrubbing_status(struct nvgpu_falcon *flcn); -int nvgpu_flcn_mem_scrub_wait(struct nvgpu_falcon *flcn); -bool nvgpu_flcn_get_cpu_halted_status(struct nvgpu_falcon *flcn); -bool nvgpu_flcn_get_idle_status(struct nvgpu_falcon *flcn); -int nvgpu_flcn_copy_from_emem(struct nvgpu_falcon *flcn, +bool nvgpu_falcon_get_mem_scrubbing_status(struct nvgpu_falcon *flcn); +int nvgpu_falcon_mem_scrub_wait(struct nvgpu_falcon *flcn); +bool nvgpu_falcon_get_cpu_halted_status(struct nvgpu_falcon *flcn); +bool nvgpu_falcon_get_idle_status(struct nvgpu_falcon *flcn); +int nvgpu_falcon_copy_from_emem(struct nvgpu_falcon *flcn, u32 src, u8 *dst, u32 size, u8 port); -int nvgpu_flcn_copy_to_emem(struct nvgpu_falcon *flcn, +int nvgpu_falcon_copy_to_emem(struct nvgpu_falcon *flcn, u32 dst, u8 *src, u32 size, u8 port); -int nvgpu_flcn_copy_from_dmem(struct nvgpu_falcon *flcn, +int nvgpu_falcon_copy_from_dmem(struct nvgpu_falcon *flcn, u32 src, u8 *dst, u32 size, u8 port); -int nvgpu_flcn_copy_to_dmem(struct nvgpu_falcon *flcn, +int nvgpu_falcon_copy_to_dmem(struct nvgpu_falcon *flcn, u32 dst, u8 *src, u32 size, u8 port); -int nvgpu_flcn_copy_to_imem(struct nvgpu_falcon *flcn, +int nvgpu_falcon_copy_to_imem(struct nvgpu_falcon *flcn, u32 dst, u8 *src, u32 size, u8 port, bool sec, u32 tag); -int nvgpu_flcn_copy_from_imem(struct nvgpu_falcon *flcn, +int nvgpu_falcon_copy_from_imem(struct nvgpu_falcon *flcn, u32 src, u8 *dst, u32 size, u8 port); -int nvgpu_flcn_dma_copy(struct nvgpu_falcon *flcn, +int nvgpu_falcon_dma_copy(struct nvgpu_falcon *flcn, struct nvgpu_falcon_dma_info *dma_info); -u32 nvgpu_flcn_mailbox_read(struct nvgpu_falcon *flcn, u32 mailbox_index); -void nvgpu_flcn_mailbox_write(struct nvgpu_falcon *flcn, u32 mailbox_index, +u32 nvgpu_falcon_mailbox_read(struct nvgpu_falcon *flcn, u32 mailbox_index); +void nvgpu_falcon_mailbox_write(struct nvgpu_falcon *flcn, u32 mailbox_index, u32 data); -int nvgpu_flcn_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector); -void nvgpu_flcn_print_dmem(struct nvgpu_falcon *flcn, u32 src, u32 size); -void nvgpu_flcn_print_imem(struct nvgpu_falcon *flcn, u32 src, u32 size); -void nvgpu_flcn_dump_stats(struct nvgpu_falcon *flcn); -int nvgpu_flcn_bl_bootstrap(struct nvgpu_falcon *flcn, +int nvgpu_falcon_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector); +void nvgpu_falcon_print_dmem(struct nvgpu_falcon *flcn, u32 src, u32 size); +void nvgpu_falcon_print_imem(struct nvgpu_falcon *flcn, u32 src, u32 size); +void nvgpu_falcon_dump_stats(struct nvgpu_falcon *flcn); +int nvgpu_falcon_bl_bootstrap(struct nvgpu_falcon *flcn, struct nvgpu_falcon_bl_info *bl_info); /* queue public functions */ -int nvgpu_flcn_queue_init(struct nvgpu_falcon *flcn, +int nvgpu_falcon_queue_init(struct nvgpu_falcon *flcn, struct nvgpu_falcon_queue *queue); -bool nvgpu_flcn_queue_is_empty(struct nvgpu_falcon *flcn, +bool nvgpu_falcon_queue_is_empty(struct nvgpu_falcon *flcn, struct nvgpu_falcon_queue *queue); -int nvgpu_flcn_queue_rewind(struct nvgpu_falcon *flcn, +int nvgpu_falcon_queue_rewind(struct nvgpu_falcon *flcn, struct nvgpu_falcon_queue *queue); -int nvgpu_flcn_queue_pop(struct nvgpu_falcon *flcn, +int nvgpu_falcon_queue_pop(struct nvgpu_falcon *flcn, struct nvgpu_falcon_queue *queue, void *data, u32 size, u32 *bytes_read); -int nvgpu_flcn_queue_push(struct nvgpu_falcon *flcn, +int nvgpu_falcon_queue_push(struct nvgpu_falcon *flcn, struct nvgpu_falcon_queue *queue, void *data, u32 size); -void nvgpu_flcn_queue_free(struct nvgpu_falcon *flcn, +void nvgpu_falcon_queue_free(struct nvgpu_falcon *flcn, struct nvgpu_falcon_queue *queue); -int nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id); +int nvgpu_falcon_sw_init(struct gk20a *g, u32 flcn_id); #endif /* NVGPU_FALCON_H */ diff --git a/drivers/gpu/nvgpu/os/linux/gk20a.c b/drivers/gpu/nvgpu/os/linux/gk20a.c index b96d8cdaf..39c0ca8ac 100644 --- a/drivers/gpu/nvgpu/os/linux/gk20a.c +++ b/drivers/gpu/nvgpu/os/linux/gk20a.c @@ -153,27 +153,27 @@ int gk20a_finalize_poweron(struct gk20a *g) } /* init interface layer support for PMU falcon */ - err = nvgpu_flcn_sw_init(g, FALCON_ID_PMU); + err = nvgpu_falcon_sw_init(g, FALCON_ID_PMU); if (err != 0) { nvgpu_err(g, "failed to sw init FALCON_ID_PMU"); goto done; } - err = nvgpu_flcn_sw_init(g, FALCON_ID_SEC2); + err = nvgpu_falcon_sw_init(g, FALCON_ID_SEC2); if (err != 0) { nvgpu_err(g, "failed to sw init FALCON_ID_SEC2"); goto done; } - err = nvgpu_flcn_sw_init(g, FALCON_ID_NVDEC); + err = nvgpu_falcon_sw_init(g, FALCON_ID_NVDEC); if (err != 0) { nvgpu_err(g, "failed to sw init FALCON_ID_NVDEC"); goto done; } - err = nvgpu_flcn_sw_init(g, FALCON_ID_GSPLITE); + err = nvgpu_falcon_sw_init(g, FALCON_ID_GSPLITE); if (err != 0) { nvgpu_err(g, "failed to sw init FALCON_ID_GSPLITE"); goto done; } - err = nvgpu_flcn_sw_init(g, FALCON_ID_FECS); + err = nvgpu_falcon_sw_init(g, FALCON_ID_FECS); if (err != 0) { nvgpu_err(g, "failed to sw init FALCON_ID_FECS"); goto done; diff --git a/drivers/gpu/nvgpu/tu104/sec2_tu104.c b/drivers/gpu/nvgpu/tu104/sec2_tu104.c index 3b9dcd284..b68826339 100644 --- a/drivers/gpu/nvgpu/tu104/sec2_tu104.c +++ b/drivers/gpu/nvgpu/tu104/sec2_tu104.c @@ -199,7 +199,7 @@ static int tu104_sec2_flcn_bl_bootstrap(struct gk20a *g, data |= (1U << 3U); gk20a_writel(g, psec_falcon_engctl_r(), data); - return nvgpu_flcn_bl_bootstrap(&g->sec2_flcn, bl_info); + return nvgpu_falcon_bl_bootstrap(&g->sec2_flcn, bl_info); } int tu104_sec2_setup_hw_and_bl_bootstrap(struct gk20a *g, @@ -210,7 +210,7 @@ int tu104_sec2_setup_hw_and_bl_bootstrap(struct gk20a *g, nvgpu_log_fn(g, " "); - nvgpu_flcn_reset(&g->sec2_flcn); + nvgpu_falcon_reset(&g->sec2_flcn); data = gk20a_readl(g, psec_fbif_ctl_r()); data |= psec_fbif_ctl_allow_phys_no_ctx_allow_f(); @@ -314,7 +314,7 @@ void tu104_sec2_enable_irq(struct nvgpu_sec2 *sec2, bool enable) u32 intr_mask; u32 intr_dest; - nvgpu_flcn_set_irq(&g->sec2_flcn, false, 0x0, 0x0); + nvgpu_falcon_set_irq(&g->sec2_flcn, false, 0x0, 0x0); if (enable) { /* dest 0=falcon, 1=host; level 0=irq0, 1=irq1 */ @@ -347,7 +347,7 @@ void tu104_sec2_enable_irq(struct nvgpu_sec2 *sec2, bool enable) psec_falcon_irqmset_swgen0_f(1) | psec_falcon_irqmset_swgen1_f(1); - nvgpu_flcn_set_irq(&g->sec2_flcn, true, intr_mask, intr_dest); + nvgpu_falcon_set_irq(&g->sec2_flcn, true, intr_mask, intr_dest); } } @@ -395,7 +395,7 @@ void tu104_sec2_isr(struct gk20a *g) if ((intr & psec_falcon_irqstat_halt_true_f()) != 0U) { nvgpu_err(g, "sec2 halt intr not implemented"); - nvgpu_flcn_dump_stats(&g->sec2_flcn); + nvgpu_falcon_dump_stats(&g->sec2_flcn); } if ((intr & psec_falcon_irqstat_exterr_true_f()) != 0U) { nvgpu_err(g, @@ -418,7 +418,7 @@ void tu104_sec2_isr(struct gk20a *g) if (recheck) { queue = &sec2->queue[SEC2_NV_MSGQ_LOG_ID]; - if (!nvgpu_flcn_queue_is_empty(sec2->flcn, queue)) { + if (!nvgpu_falcon_queue_is_empty(sec2->flcn, queue)) { gk20a_writel(g, psec_falcon_irqsset_r(), psec_falcon_irqsset_swgen0_set_f()); }