gpu: nvgpu: gp10b: Install gp10b access map

Bug 1692373

Change-Id: I63bb1f8a40fe5d2c7b61440c989b78e4cb3ece98
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/812351
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
This commit is contained in:
Terje Bergstrom
2015-10-06 10:58:54 -07:00
committed by Deepak Nibade
parent 1cde817120
commit fd624a1f4e

View File

@@ -1066,6 +1066,23 @@ static void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
tegra_fuse_writel(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0);
}
static void gr_gp10b_get_access_map(struct gk20a *g,
u32 **whitelist, int *num_entries)
{
static u32 wl_addr_gp10b[] = {
/* this list must be sorted (low to high) */
0x404468, /* gr_pri_mme_max_instructions */
0x418800, /* gr_pri_gpcs_setup_debug */
0x419a04, /* gr_pri_gpcs_tpcs_tex_lod_dbg */
0x419a08, /* gr_pri_gpcs_tpcs_tex_samp_dbg */
0x419e10, /* gr_pri_gpcs_tpcs_sm_dbgr_control0 */
0x419f78, /* gr_pri_gpcs_tpcs_sm_disp_ctrl */
};
*whitelist = wl_addr_gp10b;
*num_entries = ARRAY_SIZE(wl_addr_gp10b);
}
void gp10b_init_gr(struct gpu_ops *gops)
{
gm20b_init_gr(gops);
@@ -1095,4 +1112,5 @@ void gp10b_init_gr(struct gpu_ops *gops)
gops->gr.wait_empty = gr_gp10b_wait_empty;
gops->gr.init_cyclestats = gr_gp10b_init_cyclestats;
gops->gr.set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask;
gops->gr.get_access_map = gr_gp10b_get_access_map;
}