gpu: nvgpu: rename fifo_eng_timeout_us

Rename fifo_eng_timeout_us to ctxsw_timeout_period_ms for
clarity.

JIRA NVGPU-1312

Change-Id: I23faff3df7160c1193f797ac03769ef2ecf4449e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2076776
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/fifo/channel.c

@@ -1461,8 +1461,7 @@ bool nvgpu_channel_check_ctxsw_timeout(struct channel_gk20a *ch,
 	struct gk20a *g = ch->g;
 
 	recover = nvgpu_channel_update_and_check_ctxsw_timeout(ch,
-			g->fifo_eng_timeout_us / 1000U,
-			&progress);
+			g->ctxsw_timeout_period_ms, &progress);
 	*verbose = ch->ctxsw_timeout_debug_dump;
 	*ms = ch->ctxsw_timeout_accumulated_ms;
 	if (recover) {

drivers/gpu/nvgpu/common/fifo/tsg.c

@@ -420,7 +420,7 @@ bool nvgpu_tsg_check_ctxsw_timeout(struct tsg_gk20a *tsg,
 	struct gk20a *g = tsg->g;
 
 	*verbose = false;
-	*ms = g->fifo_eng_timeout_us / 1000U;
+	*ms = g->ctxsw_timeout_period_ms;
 
 	nvgpu_rwsem_down_read(&tsg->ch_list_lock);
 
@@ -463,7 +463,7 @@ bool nvgpu_tsg_check_ctxsw_timeout(struct tsg_gk20a *tsg,
 		nvgpu_log_info(g, "progress on tsg=%d ch=%d",
 				tsg->tsgid, ch->chid);
 		gk20a_channel_put(ch);
-		*ms = g->fifo_eng_timeout_us / 1000U;
+		*ms = g->ctxsw_timeout_period_ms;
 		nvgpu_tsg_set_ctxsw_timeout_accumulated_ms(tsg, *ms);
 	}
 

drivers/gpu/nvgpu/gk20a/fifo_gk20a.c

@@ -1392,10 +1392,10 @@ static u32 gk20a_fifo_get_preempt_timeout(struct gk20a *g)
 	/* Use fifo_eng_timeout converted to ms for preempt
 	 * polling. gr_idle_timeout i.e 3000 ms is and not appropriate
 	 * for polling preempt done as context switch timeout gets
-	 * triggered every 100 ms and context switch recovery
-	 * happens every 3000 ms */
+	 * triggered every ctxsw_timeout_period_ms.
+	 */
 
-	return g->fifo_eng_timeout_us / 1000U;
+	return g->ctxsw_timeout_period_ms;
 }
 
 int gk20a_fifo_is_preempt_pending(struct gk20a *g, u32 id,

drivers/gpu/nvgpu/gk20a/fifo_gk20a.h

@@ -55,8 +55,6 @@ struct tsg_gk20a;
 #define RC_YES				1U
 #define RC_NO				0U
 
-#define GRFIFO_TIMEOUT_CHECK_PERIOD_US 100000U
-
 #define NVGPU_FIFO_DEFAULT_TIMESLICE_TIMEOUT	128UL
 #define NVGPU_FIFO_DEFAULT_TIMESLICE_SCALE	3UL
 

drivers/gpu/nvgpu/gv100/fifo_gv100.c

@@ -35,7 +35,7 @@
 
 u32 gv100_fifo_get_preempt_timeout(struct gk20a *g)
 {
-	return g->fifo_eng_timeout_us / 1000U;
+	return g->ctxsw_timeout_period_ms;
 }
 
 void gv100_apply_ctxsw_timeout_intr(struct gk20a *g)

drivers/gpu/nvgpu/gv11b/fifo_gv11b.c

@@ -254,10 +254,10 @@ u32 gv11b_fifo_get_preempt_timeout(struct gk20a *g)
 {
 	/* using gr_idle_timeout for polling pdma/eng/runlist
 	 * might kick in timeout handler in the cases where
-	 * preempt is stuck. Use fifo_eng_timeout converted to ms
+	 * preempt is stuck. Use ctxsw_timeout_period_ms
 	 * for preempt polling */
 
-	return g->fifo_eng_timeout_us / 1000U ;
+	return g->ctxsw_timeout_period_ms;
 }
 
 static int gv11b_fifo_poll_pbdma_chan_status(struct gk20a *g, u32 id,

drivers/gpu/nvgpu/hal/fifo/fifo_intr_gk20a.c

@@ -78,7 +78,8 @@ void gk20a_fifo_intr_0_enable(struct gk20a *g, bool enable)
 	if (g->ops.fifo.apply_ctxsw_timeout_intr != NULL) {
 		g->ops.fifo.apply_ctxsw_timeout_intr(g);
 	} else {
-		timeout = g->fifo_eng_timeout_us;
+		/* timeout is in us. Enable ctxsw timeout */
+		timeout = g->ctxsw_timeout_period_ms * 1000U;
 		timeout = scale_ptimer(timeout,
 			ptimer_scalingfactor10x(g->ptimer_src_freq));
 		timeout |= fifo_eng_timeout_detection_enabled_f();

drivers/gpu/nvgpu/hal/fifo/fifo_intr_gv11b.c

@@ -95,8 +95,8 @@ void gv11b_fifo_intr_0_enable(struct gk20a *g, bool enable)
 	nvgpu_writel(g, fifo_intr_ctxsw_timeout_r(), ~U32(0U));
 
 	if (nvgpu_platform_is_silicon(g)) {
-		/* enable ctxsw timeout */
-		timeout = g->fifo_eng_timeout_us;
+		/* timeout is in us. Enable ctxsw timeout */
+		timeout = g->ctxsw_timeout_period_ms * 1000U;
 		timeout = scale_ptimer(timeout,
 			ptimer_scalingfactor10x(g->ptimer_src_freq));
 		timeout |= fifo_eng_ctxsw_timeout_detection_enabled_f();

drivers/gpu/nvgpu/include/nvgpu/fifo.h

@@ -37,6 +37,8 @@
 
 #define INVAL_ID			(~U32(0U))
 
+#define CTXSW_TIMEOUT_PERIOD_MS		100U
+
 struct gk20a;
 
 struct nvgpu_channel_hw_state {

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -1884,8 +1884,9 @@ struct gk20a {
 #endif
 	u32 gr_idle_timeout_default;
 	bool timeouts_disabled_by_user;
+
 	unsigned int ch_wdt_init_limit_ms;
-	u32 fifo_eng_timeout_us;
+	u32 ctxsw_timeout_period_ms;
 
 	struct nvgpu_mutex power_lock;
 

drivers/gpu/nvgpu/os/linux/driver_common.c

@@ -123,7 +123,7 @@ static void nvgpu_init_timeout(struct gk20a *g)
 		g->gr_idle_timeout_default = (u32)ULONG_MAX;
 	}
 	g->ch_wdt_init_limit_ms = platform->ch_wdt_init_limit_ms;
-	g->fifo_eng_timeout_us = GRFIFO_TIMEOUT_CHECK_PERIOD_US;
+	g->ctxsw_timeout_period_ms = CTXSW_TIMEOUT_PERIOD_MS;
 }
 
 static void nvgpu_init_timeslice(struct gk20a *g)