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gpu: nvgpu: refactor interrupt handling
JIRA: EVLR-1004 (*) Refactor the non-stalling interrupt path to execute clear on the top half, so on dGPU case processing of stalling interrupts does not block non-stalling one. (*) Use a worker thread to do semaphore wakeups and allow batching of the non-stalling operations. (*) Fix a bug where some gpus will not properly track the completion of interrupts, preventing safe driver unloads Change-Id: Icc90a3acba544c97ec6a9285ab235d337ab9eefa Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1312796 Reviewed-on: http://git-master/r/1320848 GVS: Gerrit_Virtual_Submit Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
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@@ -2377,7 +2377,7 @@ void gk20a_fifo_isr(struct gk20a *g)
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return;
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}
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void gk20a_fifo_nonstall_isr(struct gk20a *g)
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int gk20a_fifo_nonstall_isr(struct gk20a *g)
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{
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u32 fifo_intr = gk20a_readl(g, fifo_intr_0_r());
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u32 clear_intr = 0;
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@@ -2389,9 +2389,7 @@ void gk20a_fifo_nonstall_isr(struct gk20a *g)
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gk20a_writel(g, fifo_intr_0_r(), clear_intr);
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gk20a_channel_semaphore_wakeup(g, false);
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return;
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return gk20a_nonstall_ops_wakeup_semaphore;
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}
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void gk20a_fifo_issue_preempt(struct gk20a *g, u32 id, bool is_tsg)
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