gpu: nvgpu: refactor interrupt handling

JIRA: EVLR-1004

(*) Refactor the non-stalling interrupt path to execute clear on the
top half, so on dGPU case processing of stalling interrupts does not
block non-stalling one.
(*) Use a worker thread to do semaphore wakeups and allow batching of
the non-stalling operations.
(*) Fix a bug where some gpus will not properly track the completion
of interrupts, preventing safe driver unloads

Change-Id: Icc90a3acba544c97ec6a9285ab235d337ab9eefa
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1312796
Reviewed-on: http://git-master/r/1320848
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
This commit is contained in:
David Nieto
2017-02-06 15:44:55 -08:00
committed by mobile promotions
parent 57dafc08a5
commit fe2b83ef4d
13 changed files with 139 additions and 126 deletions

View File

@@ -2377,7 +2377,7 @@ void gk20a_fifo_isr(struct gk20a *g)
return;
}
void gk20a_fifo_nonstall_isr(struct gk20a *g)
int gk20a_fifo_nonstall_isr(struct gk20a *g)
{
u32 fifo_intr = gk20a_readl(g, fifo_intr_0_r());
u32 clear_intr = 0;
@@ -2389,9 +2389,7 @@ void gk20a_fifo_nonstall_isr(struct gk20a *g)
gk20a_writel(g, fifo_intr_0_r(), clear_intr);
gk20a_channel_semaphore_wakeup(g, false);
return;
return gk20a_nonstall_ops_wakeup_semaphore;
}
void gk20a_fifo_issue_preempt(struct gk20a *g, u32 id, bool is_tsg)