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gpu: nvgpu: refactor interrupt handling

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JIRA: EVLR-1004

(*) Refactor the non-stalling interrupt path to execute clear on the
top half, so on dGPU case processing of stalling interrupts does not
block non-stalling one.
(*) Use a worker thread to do semaphore wakeups and allow batching of
the non-stalling operations.
(*) Fix a bug where some gpus will not properly track the completion
of interrupts, preventing safe driver unloads

Change-Id: Icc90a3acba544c97ec6a9285ab235d337ab9eefa
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1312796
Reviewed-on: http://git-master/r/1320848
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
This commit is contained in:
David Nieto
2017-02-06 15:44:55 -08:00
committed by mobile promotions
parent 57dafc08a5
commit fe2b83ef4d
13 changed files with 139 additions and 126 deletions
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4
drivers/gpu/nvgpu/pci.c
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@@ -236,8 +236,7 @@ static irqreturn_t nvgpu_pci_isr(int irq, void *dev_id)
g->ops.xve.rearm_msi(g);
#endif
return (ret_stall == IRQ_NONE && ret_nonstall == IRQ_NONE) ?
IRQ_NONE : IRQ_WAKE_THREAD;
return (ret_stall == IRQ_NONE) ? ret_nonstall : IRQ_WAKE_THREAD;
}
static irqreturn_t nvgpu_pci_intr_thread(int irq, void *dev_id)
@@ -245,7 +244,6 @@ static irqreturn_t nvgpu_pci_intr_thread(int irq, void *dev_id)
struct gk20a *g = dev_id;
g->ops.mc.isr_thread_stall(g);
g->ops.mc.isr_thread_nonstall(g);
return IRQ_HANDLED;
}