diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h
index cf60ae51c..b8795632b 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h
@@ -632,6 +632,10 @@ static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void)
 {
 	return 0x200000U;
 }
+static inline u32 pwr_pmu_idle_mask_1_r(u32 i)
+{
+	return 0x0010aa34U + i*8U;
+}
 static inline u32 pwr_pmu_idle_count_r(u32 i)
 {
 	return 0x0010a508U + i*16U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h
index 7b339ae57..a7c409de6 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h
@@ -676,6 +676,10 @@ static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void)
 {
 	return 0x200000U;
 }
+static inline u32 pwr_pmu_idle_mask_1_r(u32 i)
+{
+	return 0x0010aa34U + i*8U;
+}
 static inline u32 pwr_pmu_idle_count_r(u32 i)
 {
 	return 0x0010a508U + i*16U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h
index 75f1c0469..f067be7ed 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h
@@ -680,6 +680,10 @@ static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void)
 {
 	return 0x200000U;
 }
+static inline u32 pwr_pmu_idle_mask_1_r(u32 i)
+{
+	return 0x0010aa34U + i*8U;
+}
 static inline u32 pwr_pmu_idle_count_r(u32 i)
 {
 	return 0x0010a508U + i*16U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h
index 03affe8e6..1cda12deb 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h
@@ -840,6 +840,14 @@ static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void)
 {
 	return 0x200000U;
 }
+static inline u32 pwr_pmu_idle_mask_1_r(u32 i)
+{
+	return 0x0010aa34U + i*8U;
+}
+static inline u32 pwr_pmu_idle_mask_2_r(u32 i)
+{
+	return 0x0010a840U + i*4U;
+}
 static inline u32 pwr_pmu_idle_count_r(u32 i)
 {
 	return 0x0010a508U + i*16U;
@@ -936,6 +944,10 @@ static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i)
 {
 	return 0x0010a9f4U + i*8U;
 }
+static inline u32 pwr_pmu_idle_mask_2_supp_r(u32 i)
+{
+	return 0x0010a690U + i*4U;
+}
 static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i)
 {
 	return 0x0010aa30U + i*8U;