nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-23 01:50:07 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: remove nvgpu_preemption_modes_rec struct

Browse Source 
g->ops.gr.get_preemption_mode_flags() hal is used to fetch information
on supported preemption modes and default preemption mode
Temporary struct nvgpu_preemption_modes_rec is used for this purpose
and is defined in gk20a/gr_gk20a.h right now.

Split above hal into two separate hals and move them to hal.gr.init unit
g->ops.gr.init.get_supported__preemption_modes()
g->ops.gr.init.get_default_preemption_modes()

These hals now return respective flags in pointers passed in function
parameter list, so there is no need to use temporary structure anymore
Hence delete struct nvgpu_preemption_modes_rec

Implement gm20b/gp10b chip specific hals in hal.gr.init unit.
Delete g->ops.gr.get_preemption_mode_flags() hal

Jira NVGPU-3126

Change-Id: I84f507fcd8d122bb7f0ecf697e8b4f16c9339ce1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2102455
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2019-04-19 17:14:10 +05:30
committed by mobile promotions
parent 55615829e5
commit fed6ee1afc
18 changed files with 89 additions and 63 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -148,7 +148,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.clear_sm_error_state = vgpu_gr_clear_sm_error_state,
.suspend_contexts = vgpu_gr_suspend_contexts,
.resume_contexts = vgpu_gr_resume_contexts,
.get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
.trigger_suspend = NULL,
.wait_for_pause = gr_gk20a_wait_for_pause,
.resume_from_pause = NULL,
@@ -352,6 +351,10 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.commit_cbes_reserve =
gp10b_gr_init_commit_cbes_reserve,
.detect_sm_arch = vgpu_gr_detect_sm_arch,
.get_supported__preemption_modes =
gp10b_gr_init_get_supported_preemption_modes,
.get_default_preemption_modes =
gp10b_gr_init_get_default_preemption_modes,
},
},
.class = {

5
drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -174,7 +174,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.clear_sm_error_state = vgpu_gr_clear_sm_error_state,
.suspend_contexts = vgpu_gr_suspend_contexts,
.resume_contexts = vgpu_gr_resume_contexts,
.get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
.trigger_suspend = NULL,
.wait_for_pause = gr_gk20a_wait_for_pause,
.resume_from_pause = NULL,
@@ -406,6 +405,10 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.gfxp_wfi_timeout =
gv11b_gr_init_commit_gfxp_wfi_timeout,
.detect_sm_arch = vgpu_gr_detect_sm_arch,
.get_supported__preemption_modes =
gp10b_gr_init_get_supported_preemption_modes,
.get_default_preemption_modes =
gp10b_gr_init_get_default_preemption_modes,
},
.intr = {
.handle_gcc_exception =

8
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
View File

@@ -64,14 +64,6 @@ struct gk20a_cs_snapshot_client;
struct gk20a_cs_snapshot;
#endif
struct nvgpu_preemption_modes_rec {
u32 graphics_preemption_mode_flags; /* supported preemption modes */
u32 compute_preemption_mode_flags; /* supported preemption modes */
u32 default_graphics_preempt_mode; /* default mode */
u32 default_compute_preempt_mode; /* default mode */
};
struct nvgpu_warpstate {
u64 valid_warps[2];
u64 trapped_warps[2];

17
drivers/gpu/nvgpu/gm20b/gr_gm20b.c
View File

@@ -723,23 +723,6 @@ fail:
return err;
}
int gr_gm20b_get_preemption_mode_flags(struct gk20a *g,
struct nvgpu_preemption_modes_rec *preemption_modes_rec)
{
preemption_modes_rec->graphics_preemption_mode_flags =
NVGPU_PREEMPTION_MODE_GRAPHICS_WFI;
preemption_modes_rec->compute_preemption_mode_flags = (
NVGPU_PREEMPTION_MODE_COMPUTE_WFI |
NVGPU_PREEMPTION_MODE_COMPUTE_CTA);
preemption_modes_rec->default_graphics_preempt_mode =
NVGPU_PREEMPTION_MODE_GRAPHICS_WFI;
preemption_modes_rec->default_compute_preempt_mode =
NVGPU_PREEMPTION_MODE_COMPUTE_CTA;
return 0;
}
void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
u32 global_esr)
{

2
drivers/gpu/nvgpu/gm20b/gr_gm20b.h
View File

@@ -68,8 +68,6 @@ int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc,
u32 tpc, u32 sm, struct channel_gk20a *fault_ch);
int gm20b_gr_clear_sm_error_state(struct gk20a *g,
struct channel_gk20a *ch, u32 sm_id);
int gr_gm20b_get_preemption_mode_flags(struct gk20a *g,
struct nvgpu_preemption_modes_rec *preemption_modes_rec);
void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
u32 global_esr);
u32 gr_gm20b_get_pmm_per_chiplet_offset(void);

19
drivers/gpu/nvgpu/gp10b/gr_gp10b.c
View File

@@ -1167,22 +1167,3 @@ enable_ch:
return err;
}
int gr_gp10b_get_preemption_mode_flags(struct gk20a *g,
struct nvgpu_preemption_modes_rec *preemption_modes_rec)
{
preemption_modes_rec->graphics_preemption_mode_flags = (
NVGPU_PREEMPTION_MODE_GRAPHICS_WFI |
NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP);
preemption_modes_rec->compute_preemption_mode_flags = (
NVGPU_PREEMPTION_MODE_COMPUTE_WFI |
NVGPU_PREEMPTION_MODE_COMPUTE_CTA |
NVGPU_PREEMPTION_MODE_COMPUTE_CILP);
preemption_modes_rec->default_graphics_preempt_mode =
NVGPU_PREEMPTION_MODE_GRAPHICS_WFI;
preemption_modes_rec->default_compute_preempt_mode =
NVGPU_PREEMPTION_MODE_COMPUTE_WFI;
return 0;
}

2
drivers/gpu/nvgpu/gp10b/gr_gp10b.h
View File

@@ -82,8 +82,6 @@ int gr_gp10b_suspend_contexts(struct gk20a *g,
int *ctx_resident_ch_fd);
int gr_gp10b_set_boosted_ctx(struct channel_gk20a *ch,
bool boost);
int gr_gp10b_get_preemption_mode_flags(struct gk20a *g,
struct nvgpu_preemption_modes_rec *preemption_modes_rec);
int gp10b_gr_fuse_override(struct gk20a *g);
int gr_gp10b_init_preemption_state(struct gk20a *g);
bool gr_gp10b_suspend_context(struct channel_gk20a *ch,

15
drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c
View File

@@ -1110,3 +1110,18 @@ void gm20b_gr_init_detect_sm_arch(struct gk20a *g)
gr_gpc0_tpc0_sm_arch_warp_count_v(v);
}
void gm20b_gr_init_get_supported_preemption_modes(
u32 *graphics_preemption_mode_flags, u32 *compute_preemption_mode_flags)
{
*graphics_preemption_mode_flags = NVGPU_PREEMPTION_MODE_GRAPHICS_WFI;
*compute_preemption_mode_flags = (NVGPU_PREEMPTION_MODE_COMPUTE_WFI |
NVGPU_PREEMPTION_MODE_COMPUTE_CTA);
}
void gm20b_gr_init_get_default_preemption_modes(
u32 *default_graphics_preempt_mode, u32 *default_compute_preempt_mode)
{
*default_graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_WFI;
*default_compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CTA;
}

5
drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h
View File

@@ -99,4 +99,9 @@ u32 gm20b_gr_init_get_patch_slots(struct gk20a *g,
struct nvgpu_gr_config *config);
void gm20b_gr_init_detect_sm_arch(struct gk20a *g);
void gm20b_gr_init_get_supported_preemption_modes(
u32 *graphics_preemption_mode_flags, u32 *compute_preemption_mode_flags);
void gm20b_gr_init_get_default_preemption_modes(
u32 *default_graphics_preempt_mode, u32 *default_compute_preempt_mode);
#endif /* NVGPU_GR_INIT_GM20B_H */

16
drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c
View File

@@ -591,3 +591,19 @@ void gp10b_gr_init_commit_cbes_reserve(struct gk20a *g,
patch);
}
void gp10b_gr_init_get_supported_preemption_modes(
u32 *graphics_preemption_mode_flags, u32 *compute_preemption_mode_flags)
{
*graphics_preemption_mode_flags = (NVGPU_PREEMPTION_MODE_GRAPHICS_WFI |
NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP);
*compute_preemption_mode_flags = (NVGPU_PREEMPTION_MODE_COMPUTE_WFI |
NVGPU_PREEMPTION_MODE_COMPUTE_CTA |
NVGPU_PREEMPTION_MODE_COMPUTE_CILP);
}
void gp10b_gr_init_get_default_preemption_modes(
u32 *default_graphics_preempt_mode, u32 *default_compute_preempt_mode)
{
*default_graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_WFI;
*default_compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_WFI;
}

5
drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.h
View File

@@ -71,4 +71,9 @@ void gp10b_gr_init_commit_ctxsw_spill(struct gk20a *g,
void gp10b_gr_init_commit_cbes_reserve(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx, bool patch);
void gp10b_gr_init_get_supported_preemption_modes(
u32 *graphics_preemption_mode_flags, u32 *compute_preemption_mode_flags);
void gp10b_gr_init_get_default_preemption_modes(
u32 *default_graphics_preempt_mode, u32 *default_compute_preempt_mode);
#endif /* NVGPU_GR_INIT_GP10B_H */

5
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
View File

@@ -273,7 +273,6 @@ static const struct gpu_ops gm20b_ops = {
.clear_sm_error_state = gm20b_gr_clear_sm_error_state,
.suspend_contexts = gr_gk20a_suspend_contexts,
.resume_contexts = gr_gk20a_resume_contexts,
.get_preemption_mode_flags = gr_gm20b_get_preemption_mode_flags,
.trigger_suspend = gr_gk20a_trigger_suspend,
.wait_for_pause = gr_gk20a_wait_for_pause,
.resume_from_pause = gr_gk20a_resume_from_pause,
@@ -490,6 +489,10 @@ static const struct gpu_ops gm20b_ops = {
.get_gfxp_rtv_cb_size = NULL,
.get_patch_slots = gm20b_gr_init_get_patch_slots,
.detect_sm_arch = gm20b_gr_init_detect_sm_arch,
.get_supported__preemption_modes =
gm20b_gr_init_get_supported_preemption_modes,
.get_default_preemption_modes =
gm20b_gr_init_get_default_preemption_modes,
},
.intr = {
.set_shader_exceptions =

5
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
View File

@@ -304,7 +304,6 @@ static const struct gpu_ops gp10b_ops = {
.clear_sm_error_state = gm20b_gr_clear_sm_error_state,
.suspend_contexts = gr_gp10b_suspend_contexts,
.resume_contexts = gr_gk20a_resume_contexts,
.get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
.trigger_suspend = gr_gk20a_trigger_suspend,
.wait_for_pause = gr_gk20a_wait_for_pause,
.resume_from_pause = gr_gk20a_resume_from_pause,
@@ -555,6 +554,10 @@ static const struct gpu_ops gp10b_ops = {
gp10b_gr_init_commit_cbes_reserve,
.get_patch_slots = gm20b_gr_init_get_patch_slots,
.detect_sm_arch = gm20b_gr_init_detect_sm_arch,
.get_supported__preemption_modes =
gp10b_gr_init_get_supported_preemption_modes,
.get_default_preemption_modes =
gp10b_gr_init_get_default_preemption_modes,
},
.intr = {
.set_shader_exceptions =

5
drivers/gpu/nvgpu/hal/init/hal_gv100.c
View File

@@ -409,7 +409,6 @@ static const struct gpu_ops gv100_ops = {
.clear_sm_error_state = gv11b_gr_clear_sm_error_state,
.suspend_contexts = gr_gp10b_suspend_contexts,
.resume_contexts = gr_gk20a_resume_contexts,
.get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
.trigger_suspend = gv11b_gr_sm_trigger_suspend,
.wait_for_pause = gr_gk20a_wait_for_pause,
.resume_from_pause = gv11b_gr_resume_from_pause,
@@ -690,6 +689,10 @@ static const struct gpu_ops gv100_ops = {
gv11b_gr_init_get_max_subctx_count,
.get_patch_slots = gv11b_gr_init_get_patch_slots,
.detect_sm_arch = gv11b_gr_init_detect_sm_arch,
.get_supported__preemption_modes =
gp10b_gr_init_get_supported_preemption_modes,
.get_default_preemption_modes =
gp10b_gr_init_get_default_preemption_modes,
},
.intr = {
.set_shader_exceptions =

5
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -380,7 +380,6 @@ static const struct gpu_ops gv11b_ops = {
.clear_sm_error_state = gv11b_gr_clear_sm_error_state,
.suspend_contexts = gr_gp10b_suspend_contexts,
.resume_contexts = gr_gk20a_resume_contexts,
.get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
.trigger_suspend = gv11b_gr_sm_trigger_suspend,
.wait_for_pause = gr_gk20a_wait_for_pause,
.resume_from_pause = gv11b_gr_resume_from_pause,
@@ -667,6 +666,10 @@ static const struct gpu_ops gv11b_ops = {
gv11b_gr_init_get_max_subctx_count,
.get_patch_slots = gv11b_gr_init_get_patch_slots,
.detect_sm_arch = gv11b_gr_init_detect_sm_arch,
.get_supported__preemption_modes =
gp10b_gr_init_get_supported_preemption_modes,
.get_default_preemption_modes =
gp10b_gr_init_get_default_preemption_modes,
},
.intr = {
.set_shader_exceptions =

5
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -429,7 +429,6 @@ static const struct gpu_ops tu104_ops = {
.clear_sm_error_state = gv11b_gr_clear_sm_error_state,
.suspend_contexts = gr_gp10b_suspend_contexts,
.resume_contexts = gr_gk20a_resume_contexts,
.get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
.trigger_suspend = gv11b_gr_sm_trigger_suspend,
.wait_for_pause = gr_gk20a_wait_for_pause,
.resume_from_pause = gv11b_gr_resume_from_pause,
@@ -721,6 +720,10 @@ static const struct gpu_ops tu104_ops = {
gv11b_gr_init_get_max_subctx_count,
.get_patch_slots = gv11b_gr_init_get_patch_slots,
.detect_sm_arch = gv11b_gr_init_detect_sm_arch,
.get_supported__preemption_modes =
gp10b_gr_init_get_supported_preemption_modes,
.get_default_preemption_modes =
gp10b_gr_init_get_default_preemption_modes,
},
.intr = {
.set_shader_exceptions =

8
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -372,8 +372,6 @@ struct gpu_ops {
int (*resume_contexts)(struct gk20a *g,
struct dbg_session_gk20a *dbg_s,
int *ctx_resident_ch_fd);
int (*get_preemption_mode_flags)(struct gk20a *g,
struct nvgpu_preemption_modes_rec *preemption_modes_rec);
int (*set_ctxsw_preemption_mode)(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx,
struct vm_gk20a *vm, u32 class,
@@ -782,6 +780,12 @@ struct gpu_ops {
u32 (*get_patch_slots)(struct gk20a *g,
struct nvgpu_gr_config *config);
void (*detect_sm_arch)(struct gk20a *g);
void (*get_supported__preemption_modes)(
u32 *graphics_preemption_mode_flags,
u32 *compute_preepmtion_mode_flags);
void (*get_default_preemption_modes)(
u32 *default_graphics_preempt_mode,
u32 *default_compute_preempt_mode);
} init;
struct {

20
drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
View File

@@ -250,23 +250,31 @@ static u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags(struct gk20a *g)
static void nvgpu_set_preemption_mode_flags(struct gk20a *g,
struct nvgpu_gpu_characteristics *gpu)
{
struct nvgpu_preemption_modes_rec preemption_mode_rec;
u32 graphics_preemption_mode_flags = 0U;
u32 compute_preemption_mode_flags = 0U;
u32 default_graphics_preempt_mode = 0U;
u32 default_compute_preempt_mode = 0U;
g->ops.gr.get_preemption_mode_flags(g, &preemption_mode_rec);
g->ops.gr.init.get_supported__preemption_modes(
&graphics_preemption_mode_flags,
&compute_preemption_mode_flags);
g->ops.gr.init.get_default_preemption_modes(
&default_graphics_preempt_mode,
&default_compute_preempt_mode);
gpu->graphics_preemption_mode_flags =
nvgpu_get_ioctl_graphics_preempt_mode_flags(
preemption_mode_rec.graphics_preemption_mode_flags);
graphics_preemption_mode_flags);
gpu->compute_preemption_mode_flags =
nvgpu_get_ioctl_compute_preempt_mode_flags(
preemption_mode_rec.compute_preemption_mode_flags);
compute_preemption_mode_flags);
gpu->default_graphics_preempt_mode =
nvgpu_get_ioctl_graphics_preempt_mode(
preemption_mode_rec.default_graphics_preempt_mode);
default_graphics_preempt_mode);
gpu->default_compute_preempt_mode =
nvgpu_get_ioctl_compute_preempt_mode(
preemption_mode_rec.default_compute_preempt_mode);
default_compute_preempt_mode);
}
static long