From feebc746ca587e93edf27310edc84334217b9db2 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Tue, 3 Mar 2020 09:10:09 -0800 Subject: [PATCH] gpu: nvgpu: fix global register access list For legacy chips (gm20b, gp10b and gv11b), incorrect register offset is used for global access register list: incorrect: 0x418300, /* gr_pri_gpcs_rasterarb_line_class */ correct: 0x418380, /* gr_pri_gpcs_rasterarb_line_class */ Fix this issue by updating global access register list by using correct register offset value. NVGPU-5108 Signed-off-by: Seshendra Gadagottu Change-Id: Id6722039f8d874dbcb79732dffd727d2ff2a1a72 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306642 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: svc-mobile-cert Reviewed-by: Vinod Gopalakrishnakurup Reviewed-by: automaticguardword Reviewed-by: Deepak Nibade Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions --- drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c | 2 +- drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c | 2 +- drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c index f782f0982..d88d9c691 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c @@ -84,7 +84,7 @@ void gm20b_gr_init_get_access_map(struct gk20a *g, static u32 wl_addr_gm20b[] = { /* this list must be sorted (low to high) */ 0x404468, /* gr_pri_mme_max_instructions */ - 0x418300, /* gr_pri_gpcs_rasterarb_line_class */ + 0x418380, /* gr_pri_gpcs_rasterarb_line_class */ 0x418800, /* gr_pri_gpcs_setup_debug */ 0x418830, /* gr_pri_gpcs_setup_debug_z_gamut_offset */ 0x4188fc, /* gr_pri_gpcs_zcull_ctx_debug */ diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c index 5c3c37895..12f5a2ea7 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c @@ -44,7 +44,7 @@ void gp10b_gr_init_get_access_map(struct gk20a *g, static u32 wl_addr_gp10b[] = { /* this list must be sorted (low to high) */ 0x404468, /* gr_pri_mme_max_instructions */ - 0x418300, /* gr_pri_gpcs_rasterarb_line_class */ + 0x418380, /* gr_pri_gpcs_rasterarb_line_class */ 0x418800, /* gr_pri_gpcs_setup_debug */ 0x418830, /* gr_pri_gpcs_setup_debug_z_gamut_offset */ 0x4188fc, /* gr_pri_gpcs_zcull_ctx_debug */ diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c index f60cac682..0b27345bc 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c @@ -213,7 +213,7 @@ void gv11b_gr_init_get_access_map(struct gk20a *g, static u32 wl_addr_gv11b[] = { /* this list must be sorted (low to high) */ 0x404468, /* gr_pri_mme_max_instructions */ - 0x418300, /* gr_pri_gpcs_rasterarb_line_class */ + 0x418380, /* gr_pri_gpcs_rasterarb_line_class */ 0x418800, /* gr_pri_gpcs_setup_debug */ 0x418830, /* gr_pri_gpcs_setup_debug_z_gamut_offset */ 0x4188fc, /* gr_pri_gpcs_zcull_ctx_debug */