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gpu: nvgpu: add nvgpu_pg_elpg_protected_call macro

Browse Source 
gr_gk20a_elpg_protected_call is renamed as
nvgpu_pg_elpg_protected_call and resides in common/
power_features/pg.c

JIRA NVGPU-2014

Change-Id: Id027d9a81ca93e0d47bbeeeb537d5fcd882f68d3
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2034274
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2019-03-06 15:25:34 -08:00
committed by mobile promotions
parent c905858565
commit ffb1869144
15 changed files with 41 additions and 36 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/gpu/nvgpu/common/gr/fecs_trace/fecs_trace_gm20b.c
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@@ -23,12 +23,7 @@
#include <nvgpu/gk20a.h> #include <nvgpu/gk20a.h>
#include <nvgpu/log.h> #include <nvgpu/log.h>
#include <nvgpu/io.h> #include <nvgpu/io.h>
/* #include <nvgpu/power_features/pg.h>
* TODO:
* gr_gk20a.h is needed only for gr_gk20a_elpg_protected_call()
* remove this include when possible
*/
#include <gk20a/gr_gk20a.h>
#include "fecs_trace_gm20b.h" #include "fecs_trace_gm20b.h"
@@ -38,20 +33,20 @@
int gm20b_fecs_trace_get_read_index(struct gk20a *g) int gm20b_fecs_trace_get_read_index(struct gk20a *g)
{ {
return gr_gk20a_elpg_protected_call(g, return nvgpu_pg_elpg_protected_call(g,
nvgpu_readl(g, gr_fecs_mailbox1_r())); nvgpu_readl(g, gr_fecs_mailbox1_r()));
} }
int gm20b_fecs_trace_get_write_index(struct gk20a *g) int gm20b_fecs_trace_get_write_index(struct gk20a *g)
{ {
return gr_gk20a_elpg_protected_call(g, return nvgpu_pg_elpg_protected_call(g,
nvgpu_readl(g, gr_fecs_mailbox0_r())); nvgpu_readl(g, gr_fecs_mailbox0_r()));
} }
int gm20b_fecs_trace_set_read_index(struct gk20a *g, int index) int gm20b_fecs_trace_set_read_index(struct gk20a *g, int index)
{ {
nvgpu_log(g, gpu_dbg_ctxsw, "set read=%d", index); nvgpu_log(g, gpu_dbg_ctxsw, "set read=%d", index);
return gr_gk20a_elpg_protected_call(g, return nvgpu_pg_elpg_protected_call(g,
(nvgpu_writel(g, gr_fecs_mailbox1_r(), index), 0)); (nvgpu_writel(g, gr_fecs_mailbox1_r(), index), 0));
} }

3
drivers/gpu/nvgpu/common/gr/fecs_trace/fecs_trace_gp10b.c
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@@ -22,6 +22,7 @@
#include <nvgpu/gk20a.h> #include <nvgpu/gk20a.h>
#include <nvgpu/log.h> #include <nvgpu/log.h>
#include <nvgpu/power_features/pg.h>
#include "gk20a/gr_gk20a.h" #include "gk20a/gr_gk20a.h"
#include "fecs_trace_gp10b.h" #include "fecs_trace_gp10b.h"
@@ -44,7 +45,7 @@ int gp10b_fecs_trace_flush(struct gk20a *g)
nvgpu_log(g, gpu_dbg_fn|gpu_dbg_ctxsw, " "); nvgpu_log(g, gpu_dbg_fn|gpu_dbg_ctxsw, " ");
err = gr_gk20a_elpg_protected_call(g, err = nvgpu_pg_elpg_protected_call(g,
gr_gk20a_submit_fecs_method_op(g, op, false)); gr_gk20a_submit_fecs_method_op(g, op, false));
if (err != 0) if (err != 0)
nvgpu_err(g, "write timestamp record failed"); nvgpu_err(g, "write timestamp record failed");

3
drivers/gpu/nvgpu/common/gr/zbc/gr_zbc.c
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@@ -24,6 +24,7 @@
#include <nvgpu/io.h> #include <nvgpu/io.h>
#include <nvgpu/bug.h> #include <nvgpu/bug.h>
#include <nvgpu/string.h> #include <nvgpu/string.h>
#include <nvgpu/power_features/pg.h>
#include "gr_zbc.h" #include "gr_zbc.h"
@@ -460,7 +461,7 @@ int nvgpu_gr_zbc_set_table(struct gk20a *g, struct nvgpu_gr_zbc *zbc,
{ {
nvgpu_log_fn(g, " "); nvgpu_log_fn(g, " ");
return gr_gk20a_elpg_protected_call(g, return nvgpu_pg_elpg_protected_call(g,
nvgpu_gr_zbc_add(g, zbc, zbc_val)); nvgpu_gr_zbc_add(g, zbc, zbc_val));
} }

3
drivers/gpu/nvgpu/common/mc/mc_gm20b.c
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@@ -30,6 +30,7 @@
#include <nvgpu/gk20a.h> #include <nvgpu/gk20a.h>
#include <nvgpu/bug.h> #include <nvgpu/bug.h>
#include <nvgpu/engines.h> #include <nvgpu/engines.h>
#include <nvgpu/power_features/pg.h>
#include "mc_gm20b.h" #include "mc_gm20b.h"
@@ -53,7 +54,7 @@ void gm20b_mc_isr_stall(struct gk20a *g)
engine_enum = g->fifo.engine_info[active_engine_id].engine_enum; engine_enum = g->fifo.engine_info[active_engine_id].engine_enum;
/* GR Engine */ /* GR Engine */
if (engine_enum == NVGPU_ENGINE_GR_GK20A) { if (engine_enum == NVGPU_ENGINE_GR_GK20A) {
gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); nvgpu_pg_elpg_protected_call(g, gk20a_gr_isr(g));
} }
/* CE Engine */ /* CE Engine */

3
drivers/gpu/nvgpu/common/mc/mc_gp10b.c
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@@ -26,6 +26,7 @@
#include <nvgpu/io.h> #include <nvgpu/io.h>
#include <nvgpu/mc.h> #include <nvgpu/mc.h>
#include <nvgpu/engines.h> #include <nvgpu/engines.h>
#include <nvgpu/power_features/pg.h>
#include "mc_gp10b.h" #include "mc_gp10b.h"
@@ -109,7 +110,7 @@ void mc_gp10b_isr_stall(struct gk20a *g)
engine_enum = g->fifo.engine_info[active_engine_id].engine_enum; engine_enum = g->fifo.engine_info[active_engine_id].engine_enum;
/* GR Engine */ /* GR Engine */
if (engine_enum == NVGPU_ENGINE_GR_GK20A) { if (engine_enum == NVGPU_ENGINE_GR_GK20A) {
gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); nvgpu_pg_elpg_protected_call(g, gk20a_gr_isr(g));
} }
/* CE Engine */ /* CE Engine */

5
drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c
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@@ -40,6 +40,7 @@
#include <nvgpu/gr/zbc.h> #include <nvgpu/gr/zbc.h>
#include <nvgpu/gr/fecs_trace.h> #include <nvgpu/gr/fecs_trace.h>
#include <nvgpu/cyclestats_snapshot.h> #include <nvgpu/cyclestats_snapshot.h>
#include <nvgpu/power_features/pg.h>
#include <nvgpu/hw/gk20a/hw_gr_gk20a.h> #include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
@@ -269,7 +270,7 @@ int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags)
} }
/* load golden image */ /* load golden image */
err = gr_gk20a_elpg_protected_call(g, err = nvgpu_pg_elpg_protected_call(g,
vgpu_gr_load_golden_ctx_image(g, c->virt_ctx)); vgpu_gr_load_golden_ctx_image(g, c->virt_ctx));
if (err) { if (err) {
nvgpu_err(g, "fail to load golden ctx image"); nvgpu_err(g, "fail to load golden ctx image");
@@ -284,7 +285,7 @@ int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags)
} }
#ifdef CONFIG_GK20A_CTXSW_TRACE #ifdef CONFIG_GK20A_CTXSW_TRACE
/* for fecs bind channel */ /* for fecs bind channel */
err = gr_gk20a_elpg_protected_call(g, err = nvgpu_pg_elpg_protected_call(g,
vgpu_gr_load_golden_ctx_image(g, c->virt_ctx)); vgpu_gr_load_golden_ctx_image(g, c->virt_ctx));
if (err) { if (err) {
nvgpu_err(g, "fail to load golden ctx image"); nvgpu_err(g, "fail to load golden ctx image");

1
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
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@@ -56,6 +56,7 @@
#include <nvgpu/engine_status.h> #include <nvgpu/engine_status.h>
#include <nvgpu/engines.h> #include <nvgpu/engines.h>
#include <nvgpu/power_features/cg.h> #include <nvgpu/power_features/cg.h>
#include <nvgpu/power_features/pg.h>
#include <nvgpu/power_features/power_features.h> #include <nvgpu/power_features/power_features.h>
#include "mm_gk20a.h" #include "mm_gk20a.h"

3
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
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@@ -58,6 +58,7 @@
#include <nvgpu/engine_status.h> #include <nvgpu/engine_status.h>
#include <nvgpu/nvgpu_err.h> #include <nvgpu/nvgpu_err.h>
#include <nvgpu/power_features/cg.h> #include <nvgpu/power_features/cg.h>
#include <nvgpu/power_features/pg.h>
#include "gr_gk20a.h" #include "gr_gk20a.h"
#include "gr_pri_gk20a.h" #include "gr_pri_gk20a.h"
@@ -3920,7 +3921,7 @@ int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg, nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg,
"sm hww global 0x%08x warp 0x%08x", global_esr, warp_esr); "sm hww global 0x%08x warp 0x%08x", global_esr, warp_esr);
gr_gk20a_elpg_protected_call(g, nvgpu_pg_elpg_protected_call(g,
g->ops.gr.record_sm_error_state(g, gpc, tpc, sm, fault_ch)); g->ops.gr.record_sm_error_state(g, gpc, tpc, sm, fault_ch));
if (g->ops.gr.pre_process_sm_exception != NULL) { if (g->ops.gr.pre_process_sm_exception != NULL) {

15
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
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@@ -26,7 +26,6 @@
#include <nvgpu/types.h> #include <nvgpu/types.h>
#include <nvgpu/netlist.h> #include <nvgpu/netlist.h>
#include <nvgpu/power_features/pg.h>
#include "mm_gk20a.h" #include "mm_gk20a.h"
@@ -400,20 +399,6 @@ void gr_gk20a_init_cg_mode(struct gk20a *g, u32 cgmode, u32 mode_config);
bool gk20a_gr_sm_debugger_attached(struct gk20a *g); bool gk20a_gr_sm_debugger_attached(struct gk20a *g);
u32 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g); u32 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g);
#define gr_gk20a_elpg_protected_call(g, func) \
({ \
int err = 0; \
err = nvgpu_pg_elpg_disable(g);\
if (err != 0) {\
err = nvgpu_pg_elpg_enable(g);\
}\
if (err == 0) { \
err = (func); \
(void)nvgpu_pg_elpg_enable(g);\
} \
err; \
})
int gk20a_gr_suspend(struct gk20a *g); int gk20a_gr_suspend(struct gk20a *g);
struct nvgpu_dbg_reg_op; struct nvgpu_dbg_reg_op;

1
drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
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@@ -49,6 +49,7 @@
#include <nvgpu/pbdma_status.h> #include <nvgpu/pbdma_status.h>
#include <nvgpu/engine_status.h> #include <nvgpu/engine_status.h>
#include <nvgpu/power_features/cg.h> #include <nvgpu/power_features/cg.h>
#include <nvgpu/power_features/pg.h>
#include <nvgpu/power_features/power_features.h> #include <nvgpu/power_features/power_features.h>
#include "gk20a/fifo_gk20a.h" #include "gk20a/fifo_gk20a.h"

14
drivers/gpu/nvgpu/include/nvgpu/power_features/pg.h
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@@ -28,6 +28,20 @@
struct gk20a; struct gk20a;
#define nvgpu_pg_elpg_protected_call(g, func) \
({ \
int err = 0; \
err = nvgpu_pg_elpg_disable(g);\
if (err != 0) {\
err = nvgpu_pg_elpg_enable(g);\
}\
if (err == 0) { \
err = (func); \
(void)nvgpu_pg_elpg_enable(g);\
} \
err; \
})
int nvgpu_pg_elpg_disable(struct gk20a *g); int nvgpu_pg_elpg_disable(struct gk20a *g);
int nvgpu_pg_elpg_enable(struct gk20a *g); int nvgpu_pg_elpg_enable(struct gk20a *g);
bool nvgpu_pg_elpg_is_enabled(struct gk20a *g); bool nvgpu_pg_elpg_is_enabled(struct gk20a *g);

3
drivers/gpu/nvgpu/os/linux/debug.c
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@@ -28,6 +28,7 @@
#include "platform_gk20a.h" #include "platform_gk20a.h"
#include <nvgpu/gk20a.h> #include <nvgpu/gk20a.h>
#include <nvgpu/power_features/pg.h>
#include <linux/debugfs.h> #include <linux/debugfs.h>
#include <linux/seq_file.h> #include <linux/seq_file.h>
@@ -73,7 +74,7 @@ static int gk20a_gr_dump_regs(struct gk20a *g,
struct gk20a_debug_output *o) struct gk20a_debug_output *o)
{ {
if (g->ops.gr.dump_gr_regs) if (g->ops.gr.dump_gr_regs)
gr_gk20a_elpg_protected_call(g, g->ops.gr.dump_gr_regs(g, o)); nvgpu_pg_elpg_protected_call(g, g->ops.gr.dump_gr_regs(g, o));
return 0; return 0;
} }

3
drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
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@@ -36,6 +36,7 @@
#include <nvgpu/gr/zbc.h> #include <nvgpu/gr/zbc.h>
#include <nvgpu/channel.h> #include <nvgpu/channel.h>
#include <nvgpu/pmu/pmgr.h> #include <nvgpu/pmu/pmgr.h>
#include <nvgpu/power_features/pg.h>
#include "ioctl_ctrl.h" #include "ioctl_ctrl.h"
#include "ioctl_dbg.h" #include "ioctl_dbg.h"
@@ -1819,7 +1820,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
break; break;
case NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE: case NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE:
err = gr_gk20a_elpg_protected_call(g, err = nvgpu_pg_elpg_protected_call(g,
nvgpu_gpu_ioctl_set_debug_mode(g, (struct nvgpu_gpu_sm_debug_mode_args *)buf)); nvgpu_gpu_ioctl_set_debug_mode(g, (struct nvgpu_gpu_sm_debug_mode_args *)buf));
break; break;

3
drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
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@@ -36,6 +36,7 @@
#include <nvgpu/tsg.h> #include <nvgpu/tsg.h>
#include <nvgpu/regops.h> #include <nvgpu/regops.h>
#include <nvgpu/gr/ctx.h> #include <nvgpu/gr/ctx.h>
#include <nvgpu/power_features/pg.h>
#include <nvgpu/linux/vm.h> #include <nvgpu/linux/vm.h>
@@ -1469,7 +1470,7 @@ static int nvgpu_dbg_gpu_ioctl_clear_single_sm_error_state(
return err; return err;
} }
err = gr_gk20a_elpg_protected_call(g, err = nvgpu_pg_elpg_protected_call(g,
g->ops.gr.clear_sm_error_state(g, ch, sm_id)); g->ops.gr.clear_sm_error_state(g, ch, sm_id));
gk20a_idle(g); gk20a_idle(g);

4
drivers/gpu/nvgpu/os/linux/sysfs.c
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@@ -1061,7 +1061,7 @@ static ssize_t gfxp_wfi_timeout_count_store(struct device *dev,
if (err) if (err)
return err; return err;
err = gr_gk20a_elpg_protected_call(g, err = nvgpu_pg_elpg_protected_call(g,
g->ops.gr.init_preemption_state(g)); g->ops.gr.init_preemption_state(g));
gk20a_idle(g); gk20a_idle(g);
@@ -1091,7 +1091,7 @@ static ssize_t gfxp_wfi_timeout_unit_store(struct device *dev,
if (err) if (err)
return err; return err;
err = gr_gk20a_elpg_protected_call(g, err = nvgpu_pg_elpg_protected_call(g,
g->ops.gr.init_preemption_state(g)); g->ops.gr.init_preemption_state(g));
gk20a_idle(g); gk20a_idle(g);