gpu: nvgpu: move fifo init/deinit code to common

Add fifo sub-unit to common.fifo to handle init/deinit code
and global support functions.

Split init into:
- nvgpu_channel_setup_sw
- nvgpu_tsg_setup_sw
- nvgpu_fifo_setup_sw
- nvgpu_runlist_setup_sw
- nvgpu_engine_setup_sw
- nvgpu_userd_setup_sw
- nvgpu_pbdma_setup_sw

Split de-init into
- nvgpu_channel_cleanup_sw
- nvgpu_tsg_cleanup_sw
- nvgpu_fifo_cleanup_sw
- nvgpu_runlist_cleanup_sw
- nvgpu_engine_cleanup_sw
- nvgpu_userd_cleanup_sw
- nvgpu_pbdma_cleanup_sw

Added the following HALs
- runlist.length_max
- fifo.init_pbdma_info
- fifo.userd_entry_size

Last 2 HALs should be moved resp. to pbdma and userd sub-units,
when available.

Added vgpu implementation of above hals
- vgpu_runlist_length_max
- vgpu_userd_entry_size
- vgpu_channel_count

Use hals in vgpu_fifo_setup_sw.

Jira NVGPU-1306

Change-Id: I954f56be724eee280d7b5f171b1790d33c810470
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2029620
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/fifo/engines.c

@@ -446,4 +446,54 @@ int nvgpu_engine_wait_for_idle(struct gk20a *g)
 
 #endif /* NVGPU_ENGINE */
 
+int nvgpu_engine_setup_sw(struct gk20a *g)
+{
+	struct fifo_gk20a *f = &g->fifo;
+	int err = 0;
+	size_t size;
 
+	f->max_engines = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_ENGINES);
+	size = f->max_engines * sizeof(*f->engine_info);
+	f->engine_info = nvgpu_kzalloc(g, size);
+	if (f->engine_info == NULL) {
+		nvgpu_err(g, "no mem for engine info");
+		return -ENOMEM;
+	}
+
+	size = f->max_engines * sizeof(u32);
+	f->active_engines_list = nvgpu_kzalloc(g, size);
+	if (f->active_engines_list == NULL) {
+		nvgpu_err(g, "no mem for active engine list");
+		err = -ENOMEM;
+		goto clean_up_engine_info;
+	}
+	(void) memset(f->active_engines_list, 0xff, size);
+
+	err = g->ops.fifo.init_engine_info(f);
+	if (err != 0) {
+		nvgpu_err(g, "init engine info failed");
+		goto clean_up;
+	}
+
+	return 0;
+
+clean_up:
+	nvgpu_kfree(g, f->active_engines_list);
+	f->active_engines_list = NULL;
+
+clean_up_engine_info:
+	nvgpu_kfree(g, f->engine_info);
+	f->engine_info = NULL;
+
+	return err;
+}
+
+void nvgpu_engine_cleanup_sw(struct gk20a *g)
+{
+	struct fifo_gk20a *f = &g->fifo;
+
+	nvgpu_kfree(g, f->engine_info);
+	f->engine_info = NULL;
+	nvgpu_kfree(g, f->active_engines_list);
+	f->active_engines_list = NULL;
+}