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git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-25 02:52:51 +03:00
gpu: nvgpu: move fifo init/deinit code to common
Add fifo sub-unit to common.fifo to handle init/deinit code and global support functions. Split init into: - nvgpu_channel_setup_sw - nvgpu_tsg_setup_sw - nvgpu_fifo_setup_sw - nvgpu_runlist_setup_sw - nvgpu_engine_setup_sw - nvgpu_userd_setup_sw - nvgpu_pbdma_setup_sw Split de-init into - nvgpu_channel_cleanup_sw - nvgpu_tsg_cleanup_sw - nvgpu_fifo_cleanup_sw - nvgpu_runlist_cleanup_sw - nvgpu_engine_cleanup_sw - nvgpu_userd_cleanup_sw - nvgpu_pbdma_cleanup_sw Added the following HALs - runlist.length_max - fifo.init_pbdma_info - fifo.userd_entry_size Last 2 HALs should be moved resp. to pbdma and userd sub-units, when available. Added vgpu implementation of above hals - vgpu_runlist_length_max - vgpu_userd_entry_size - vgpu_channel_count Use hals in vgpu_fifo_setup_sw. Jira NVGPU-1306 Change-Id: I954f56be724eee280d7b5f171b1790d33c810470 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2029620 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
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mobile promotions
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parent
f087ec0826
commit
ffed5095db
@@ -221,59 +221,6 @@ static inline u32 gk20a_mmu_id_to_engine_id(struct gk20a *g, u32 fault_id)
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return active_engine_id;
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}
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static void gk20a_remove_fifo_support(struct fifo_gk20a *f)
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{
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struct gk20a *g = f->g;
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unsigned int i = 0;
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nvgpu_log_fn(g, " ");
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nvgpu_channel_worker_deinit(g);
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/*
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* Make sure all channels are closed before deleting them.
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*/
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for (; i < f->num_channels; i++) {
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struct channel_gk20a *c = f->channel + i;
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struct tsg_gk20a *tsg = f->tsg + i;
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/*
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* Could race but worst that happens is we get an error message
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* from gk20a_free_channel() complaining about multiple closes.
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*/
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if (c->referenceable) {
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__gk20a_channel_kill(c);
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}
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nvgpu_mutex_destroy(&tsg->event_id_list_lock);
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nvgpu_mutex_destroy(&c->ioctl_lock);
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nvgpu_mutex_destroy(&c->joblist.cleanup_lock);
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nvgpu_mutex_destroy(&c->joblist.pre_alloc.read_lock);
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nvgpu_mutex_destroy(&c->sync_lock);
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#if defined(CONFIG_GK20A_CYCLE_STATS)
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nvgpu_mutex_destroy(&c->cyclestate.cyclestate_buffer_mutex);
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nvgpu_mutex_destroy(&c->cs_client_mutex);
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#endif
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nvgpu_mutex_destroy(&c->dbg_s_lock);
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}
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nvgpu_vfree(g, f->channel);
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nvgpu_vfree(g, f->tsg);
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gk20a_fifo_free_userd_slabs(g);
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(void) nvgpu_vm_area_free(g->mm.bar1.vm, f->userd_gpu_va);
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f->userd_gpu_va = 0ULL;
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gk20a_fifo_delete_runlist(f);
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nvgpu_kfree(g, f->pbdma_map);
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f->pbdma_map = NULL;
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nvgpu_kfree(g, f->engine_info);
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f->engine_info = NULL;
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nvgpu_kfree(g, f->active_engines_list);
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f->active_engines_list = NULL;
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}
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u32 gk20a_fifo_intr_0_error_mask(struct gk20a *g)
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{
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u32 intr_0_error_mask =
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@@ -382,170 +329,6 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g)
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return 0;
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}
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static int nvgpu_init_runlist_enginfo(struct gk20a *g, struct fifo_gk20a *f)
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{
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struct fifo_runlist_info_gk20a *runlist;
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struct fifo_engine_info_gk20a *engine_info;
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u32 i, active_engine_id, pbdma_id, engine_id;
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nvgpu_log_fn(g, " ");
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for (i = 0; i < f->num_runlists; i++) {
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runlist = &f->active_runlist_info[i];
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for (pbdma_id = 0; pbdma_id < f->num_pbdma; pbdma_id++) {
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if ((f->pbdma_map[pbdma_id] &
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BIT32(runlist->runlist_id)) != 0U) {
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runlist->pbdma_bitmask |= BIT32(pbdma_id);
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}
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}
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nvgpu_log(g, gpu_dbg_info, "runlist %d : pbdma bitmask 0x%x",
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runlist->runlist_id, runlist->pbdma_bitmask);
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for (engine_id = 0; engine_id < f->num_engines; ++engine_id) {
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active_engine_id = f->active_engines_list[engine_id];
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engine_info = &f->engine_info[active_engine_id];
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if ((engine_info != NULL) &&
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(engine_info->runlist_id == runlist->runlist_id)) {
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runlist->eng_bitmask |= BIT(active_engine_id);
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}
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}
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nvgpu_log(g, gpu_dbg_info, "runlist %d : act eng bitmask 0x%x",
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runlist->runlist_id, runlist->eng_bitmask);
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}
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nvgpu_log_fn(g, "done");
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return 0;
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}
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int gk20a_init_fifo_setup_sw_common(struct gk20a *g)
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{
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struct fifo_gk20a *f = &g->fifo;
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unsigned int chid, i;
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int err = 0;
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nvgpu_log_fn(g, " ");
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f->g = g;
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err = nvgpu_mutex_init(&f->intr.isr.mutex);
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if (err != 0) {
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nvgpu_err(g, "failed to init isr.mutex");
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return err;
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}
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err = nvgpu_mutex_init(&f->engines_reset_mutex);
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if (err != 0) {
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nvgpu_err(g, "failed to init engines_reset_mutex");
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return err;
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}
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nvgpu_spinlock_init(&f->runlist_submit_lock);
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g->ops.fifo.init_pbdma_intr_descs(f); /* just filling in data/tables */
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f->num_channels = g->ops.channel.count(g);
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f->runlist_entry_size = g->ops.runlist.entry_size();
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f->num_runlist_entries = fifo_eng_runlist_length_max_v();
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f->num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA);
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f->max_engines = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_ENGINES);
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f->userd_entry_size = BIT16(ram_userd_base_shift_v());
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f->channel = nvgpu_vzalloc(g, f->num_channels * sizeof(*f->channel));
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f->tsg = nvgpu_vzalloc(g, f->num_channels * sizeof(*f->tsg));
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f->pbdma_map = nvgpu_kzalloc(g, f->num_pbdma * sizeof(*f->pbdma_map));
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f->engine_info = nvgpu_kzalloc(g, f->max_engines *
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sizeof(*f->engine_info));
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f->active_engines_list = nvgpu_kzalloc(g, f->max_engines * sizeof(u32));
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if (!((f->channel != NULL) &&
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(f->tsg != NULL) &&
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(f->pbdma_map != NULL) &&
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(f->engine_info != NULL) &&
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(f->active_engines_list != NULL))) {
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err = -ENOMEM;
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goto clean_up;
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}
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(void) memset(f->active_engines_list, 0xff,
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(f->max_engines * sizeof(u32)));
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/* pbdma map needs to be in place before calling engine info init */
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for (i = 0; i < f->num_pbdma; ++i) {
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f->pbdma_map[i] = gk20a_readl(g, fifo_pbdma_map_r(i));
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}
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g->ops.fifo.init_engine_info(f);
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err = nvgpu_init_runlist(g, f);
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if (err != 0) {
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nvgpu_err(g, "failed to init runlist");
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goto clean_up;
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}
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nvgpu_init_runlist_enginfo(g, f);
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if (err != 0) {
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nvgpu_err(g, "failed to init runlist engine info");
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goto clean_up;
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}
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nvgpu_init_list_node(&f->free_chs);
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err = nvgpu_mutex_init(&f->free_chs_mutex);
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if (err != 0) {
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nvgpu_err(g, "failed to init free_chs_mutex");
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goto clean_up;
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}
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for (chid = 0; chid < f->num_channels; chid++) {
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gk20a_init_channel_support(g, chid);
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gk20a_init_tsg_support(g, chid);
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}
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err = nvgpu_mutex_init(&f->tsg_inuse_mutex);
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if (err != 0) {
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nvgpu_err(g, "failed to init tsg_inuse_mutex");
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goto clean_up;
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}
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f->remove_support = gk20a_remove_fifo_support;
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f->deferred_reset_pending = false;
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err = nvgpu_mutex_init(&f->deferred_reset_mutex);
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if (err != 0) {
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nvgpu_err(g, "failed to init deferred_reset_mutex");
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goto clean_up;
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}
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err = gk20a_fifo_init_userd_slabs(g);
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if (err != 0) {
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nvgpu_err(g, "userd slabs init fail, err=%d", err);
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goto clean_up;
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}
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nvgpu_log_fn(g, "done");
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return 0;
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clean_up:
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nvgpu_err(g, "fail");
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nvgpu_vfree(g, f->channel);
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f->channel = NULL;
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nvgpu_vfree(g, f->tsg);
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f->tsg = NULL;
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nvgpu_kfree(g, f->pbdma_map);
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f->pbdma_map = NULL;
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nvgpu_kfree(g, f->engine_info);
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f->engine_info = NULL;
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nvgpu_kfree(g, f->active_engines_list);
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f->active_engines_list = NULL;
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return err;
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}
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int gk20a_fifo_init_userd_slabs(struct gk20a *g)
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{
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struct fifo_gk20a *f = &g->fifo;
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@@ -627,55 +410,6 @@ void gk20a_fifo_free_userd_slabs(struct gk20a *g)
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f->userd_slabs = NULL;
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}
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int gk20a_init_fifo_setup_sw(struct gk20a *g)
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{
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struct fifo_gk20a *f = &g->fifo;
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int err = 0;
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u32 size;
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u32 num_pages;
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nvgpu_log_fn(g, " ");
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if (f->sw_ready) {
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nvgpu_log_fn(g, "skip init");
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return 0;
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}
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err = gk20a_init_fifo_setup_sw_common(g);
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if (err != 0) {
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nvgpu_err(g, "fail: err: %d", err);
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return err;
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}
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size = f->num_channels * f->userd_entry_size;
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num_pages = DIV_ROUND_UP(size, PAGE_SIZE);
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err = nvgpu_vm_area_alloc(g->mm.bar1.vm,
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num_pages, PAGE_SIZE, &f->userd_gpu_va, 0);
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if (err != 0) {
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nvgpu_err(g, "userd gpu va allocation failed, err=%d", err);
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goto clean_slabs;
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}
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err = nvgpu_channel_worker_init(g);
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if (err != 0) {
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nvgpu_err(g, "worker init fail, err=%d", err);
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goto clean_vm_area;
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}
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f->sw_ready = true;
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nvgpu_log_fn(g, "done");
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return 0;
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clean_vm_area:
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(void) nvgpu_vm_area_free(g->mm.bar1.vm, f->userd_gpu_va);
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f->userd_gpu_va = 0ULL;
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clean_slabs:
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gk20a_fifo_free_userd_slabs(g);
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return err;
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}
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void gk20a_fifo_handle_runlist_event(struct gk20a *g)
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{
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u32 runlist_event = gk20a_readl(g, fifo_intr_runlist_r());
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@@ -708,25 +442,6 @@ int gk20a_init_fifo_setup_hw(struct gk20a *g)
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return 0;
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}
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int gk20a_init_fifo_support(struct gk20a *g)
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{
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int err;
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err = g->ops.fifo.setup_sw(g);
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if (err != 0) {
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return err;
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}
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if (g->ops.fifo.init_fifo_setup_hw != NULL) {
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err = g->ops.fifo.init_fifo_setup_hw(g);
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}
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if (err != 0) {
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return err;
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}
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return err;
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}
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/* return with a reference to the channel, caller must put it back */
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struct channel_gk20a *
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gk20a_refch_from_inst_ptr(struct gk20a *g, u64 inst_ptr)
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@@ -2881,6 +2596,11 @@ void gk20a_fifo_userd_gp_put(struct gk20a *g, struct channel_gk20a *c)
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gk20a_bar1_writel(g, (u32)addr, c->gpfifo.put);
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}
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u32 gk20a_fifo_userd_entry_size(struct gk20a *g)
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{
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return BIT32(ram_userd_base_shift_v());
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}
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u32 gk20a_fifo_pbdma_acquire_val(u64 timeout)
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{
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u32 val, exponent, mantissa;
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@@ -2944,3 +2664,26 @@ bool gk20a_fifo_find_pbdma_for_runlist(struct fifo_gk20a *f, u32 runlist_id,
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*pbdma_id = id;
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return found_pbdma_for_runlist;
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}
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int gk20a_fifo_init_pbdma_info(struct fifo_gk20a *f)
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{
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struct gk20a *g = f->g;
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u32 id;
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f->num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA);
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f->pbdma_map = nvgpu_kzalloc(g, f->num_pbdma * sizeof(*f->pbdma_map));
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if (f->pbdma_map == NULL) {
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return -ENOMEM;
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}
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for (id = 0; id < f->num_pbdma; ++id) {
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f->pbdma_map[id] = gk20a_readl(g, fifo_pbdma_map_r(id));
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}
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if (g->ops.fifo.init_pbdma_intr_descs != NULL) {
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g->ops.fifo.init_pbdma_intr_descs(f);
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}
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return 0;
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}
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