5 Commits

Author	SHA1	Message	Date
Seema Khowala	6ba1f5db3b	gpu: nvgpu: move chip specific teardown_mask/unmask_intr ... Move chip specific functions for teardown_mask_intr and teardown_unmask_intr to hal/fifo/fifo_intr_[chip].[ch] Renamed teardown_mask_intr -> intr_set_recover_mask teardown_unmask_intr -> intr_unset_recover_mask JIRA NVGPU-1314 Change-Id: If233565cbdb09d77cfebd4346edcc3fe64584355 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2093980 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-04-18 15:55:53 -07:00
Seema Khowala	66cb9495a5	gpu: nvgpu: move mmu_fault_pending ops out from mm ... Moved -mmu_fault_pending mm ops to is_mmu_fault_pending mc ops -mmu_fault_pending fb ops to is_mmu_fault_pending fb.intr ops. This is needed to check if mmu fault intr is pending for volta onwards. Added is_mmu_fault_pending fifo ops. This is needed to check if mmu fault interrupt is pending for chips prior to volta JIRA NVGPU-1313 Change-Id: Ie8e778387cd486cb19b18c4aee734c581dcd9229 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2094895 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-04-11 22:25:01 -07:00
Debarshi Dutta	ce5c43d24a	gpu: nvgpu: re-org top level pbdma interrupt handler ... fifo_pbdma_isr is moved to fifo_intr_gk20a HAL unit and renamed to gk20a_fifo_pbdma_isr. The pbdma specific handling part of the function gk20a_fifo_handle_pbdma_intr is now separated into a top level HAL function named handle_pbdma_intr. This HAL function is implemented for GM20B and all the other architectures use the same implementation. handle_pbdma_intr can accept NULL values for the parameters handled and error_notifier. gk20a_fifo_handle_pbdma_intr is called from gv11b_fifo_poll_pbdma_chan_status and gk20a_fifo_pbdma_isr. The call to gk20a_fifo_handle_pbdma_intr from gv11b_fifo_poll_pbdma_chan_status doesn't progress to recovery. Thus, the function gk20a_fifo_handle_pbdma_intr is removed to decouple pbdma handling from recovery. gv11b_fifo_poll_pbdma_chan_status now directly calls the HAL handle_pbdma_intr. For gk20a_fifo_pbdma_isr, rc_type is used to proceed to recovery by calling gk20a_fifo_pbdma_fault_rc. gk20a_fifo_pbdma_fault_rc is changed to public from static. Jira NVGPU-2950 Change-Id: I4f3597aca2317d4b745cd47bab9dd95c927160a9 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2073535 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-03-28 01:14:53 -07:00
Seema Khowala	dfafddcc21	gpu: nvgpu: move common and chip specific ctxsw timeout ... Delete apply_ctxsw_timeout_intr ops and add ctxsw_timeout_enable ops Move chip specific sched_error and ctxsw_timeout functions to hal/fifo/fifo_intr_* and hal/fifo/ctxsw_timeout_* Add nvgpu_rc_ctxsw_timeout function under common/rc/rc.c Do not check ctxsw timeout for channels that are no more bound to tsg. JIRA NVGPU-1312 Change-Id: Ide977fb60b3b72a27d9f22873f7a416c3bd1181d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2075734 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-03-25 22:47:45 -07:00
Seema Khowala	f66f3e1341	gpu: nvgpu: move fifo intr to hal/fifo ... Removed intr_0_error_mask ops Added below ops for fifo intr intr_0_enable intr_1_enable intr_0_isr intr_1_isr JIRA NVGPU-1310 Change-Id: I19bd1a380a89cffd582d6c4a0b7796a46fec5afb Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2072144 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-03-25 11:03:39 -07:00