3 Commits

Author	SHA1	Message	Date
Thomas Fleury	30591ce1a7	gpu: nvgpu: move runlist_submit_lock to runlist ... runlist_submit_lock is used by runlist unit. Move initialization to nvgpu_runlist_setup_sw. Jira NVGPU-1306 Change-Id: I8476a12b51cd0831de700c793559d46cd43b784e Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2076707 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-03-20 16:26:24 -07:00
Thomas Fleury	6729d67f59	gpu: nvgpu: vpgu: use fifo common init/deinit code ... Native and vgpu were using different paths for fifo init/deinit code. Use same nvgpu_fifo_init_support for init code: nvgpu_fifo_init_support g->ops.fifo.setup_sw vgpu_fifo_setup_sw (NEW) Use same nvgpu_fifo_remove_support for deinit code: nvgpu_fifo_remove_support (NEW) g->ops.fifo.cleanup_sw (NEW) vgpu_fifo_cleanup_sw (NEW) Also implemented gk20a_fifo_cleanup_sw for native case. Jira NVGPU-1306 Jira NVGPU-2855 Change-Id: Iefe303cc224f804a206422e2efffda9da1616d89 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2029649 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-03-18 16:56:04 -07:00
Thomas Fleury	ffed5095db	gpu: nvgpu: move fifo init/deinit code to common ... Add fifo sub-unit to common.fifo to handle init/deinit code and global support functions. Split init into: - nvgpu_channel_setup_sw - nvgpu_tsg_setup_sw - nvgpu_fifo_setup_sw - nvgpu_runlist_setup_sw - nvgpu_engine_setup_sw - nvgpu_userd_setup_sw - nvgpu_pbdma_setup_sw Split de-init into - nvgpu_channel_cleanup_sw - nvgpu_tsg_cleanup_sw - nvgpu_fifo_cleanup_sw - nvgpu_runlist_cleanup_sw - nvgpu_engine_cleanup_sw - nvgpu_userd_cleanup_sw - nvgpu_pbdma_cleanup_sw Added the following HALs - runlist.length_max - fifo.init_pbdma_info - fifo.userd_entry_size Last 2 HALs should be moved resp. to pbdma and userd sub-units, when available. Added vgpu implementation of above hals - vgpu_runlist_length_max - vgpu_userd_entry_size - vgpu_channel_count Use hals in vgpu_fifo_setup_sw. Jira NVGPU-1306 Change-Id: I954f56be724eee280d7b5f171b1790d33c810470 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2029620 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-03-14 20:35:22 -07:00