2 Commits

Author	SHA1	Message	Date
Terje Bergstrom	dec8625b88	gpu: nvgpu: Move SW scratch register read to bus ... SW scratch register is in bus register range. Move query of that register to bus HAL from bios. JIRA NVGPU-588 Change-Id: I69f35af3d5f8da3550eb68fe7d060a3ec48ce275 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730898 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2018-06-14 06:44:07 -07:00
David Nieto	f518304e0d	gpu: nvgpu: fix GV100 hal definitions ... These changes allow GV100 to init the basic HALs to pass nvgpu_submit_twod (1) Allocate fault buffer from vidmem instead of sysmem to prevent coherency issues (2) Properly enable FB (3) Fan control requires the execution of the pre-os FW, without it the SKU201 is extremely noisy JIRA: NVGPUGV100-9 Change-Id: I9b2072737e45432f957e7faae6d33bc0ab43b817 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1539926 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>	2017-10-10 12:05:41 -07:00