Added a dedicated device node to allow an
app manager to control TSG scheduling parameters:
- Get list of TSGs
- Get list of recent TSGs
- Get list of TSGs per pid
- Get TSG current scheduling parameters
- Set TSG timeslice
- Set TSG runlist interleave
Jira VFND-1586
Change-Id: I014c9d1534bce0eaea6c25ad114cf0cff317af79
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1160384
(cherry picked from commit 75ca739517cc7f7f76714b5f6a1a57c39b8cb38e)
Reviewed-on: http://git-master/r/1167021
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
This patch calculates:
-Total time spent by GPU with rails gated.
-Total time spent by GPU with rails ungated.
-Total Railgating Cycles.
and dumps this information in debugfs file.
This feature requires CONFIG_DEBUG_FS set to true.
Bug 200195100
Change-Id: I1379f11237ce4900076947e18524caaa3304c7cb
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1178308
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Set has_physical_mode if running on native linux for better performance.
Set it false if running on native gpu but on linux-hv, as the driver
can not get real physical address.
JIRA VFND-1965
Change-Id: I6e0322e64ad14d35d179a33e979157b53d77005a
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1175739
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
We currenlty initialize both runtime PM and pm_domains frameworks
and use pm_domain to control runtime power management of NvGPU
But since GPU has a separate rail, using pm_domain is not
strictly required
Hence remove pm_domain support and use runtime PM only for all
the power management
This also simplifies the code a lot
Initialization in gk20a_pm_init()
- if railgate_delay is set, set autosuspend delay of runtime PM
- try enabling runtime PM
- if runtime PM is now enabled, keep GPU railgated
- if runtime PM is not enabled, keep GPU unrailgated
- if can_railgate = false, disable runtime PM and keep
GPU unrailgated
Set gk20a_pm_ops with below callbacks for runtime PM
static const struct dev_pm_ops gk20a_pm_ops = {
.runtime_resume = gk20a_pm_runtime_resume,
.runtime_suspend = gk20a_pm_runtime_suspend,
.resume = gk20a_pm_resume,
.suspend = gk20a_pm_suspend,
}
Move gk20a_busy() to use runtime checks of pm_runtime_enabled()
instead of using compile time checks on CONFIG_PM
Clean up some pm_domain related code
Remove use of gk20a_pm_enable/disable_clk() since this
should be already done in platform specific unrailgate()/
railgate() APIs
Fix "railgate_delay" and "railgate_enable" sysfs to use
runtime PM calls
For VGPU, disable runtime PM during vgpu_pm_init()
With this, we will initialize vgpu with vgpu_pm_finalize_poweron()
upon first call to gk20a_busy()
Jira DNVGPU-57
Change-Id: I6013e33ae9bd28f35c25271af1239942a4fa0919
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1163216
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
When copying chip name to GPU characteristics limit the size of copy
to the size of target name field.
Coverity ID 33613
Change-Id: Ia538d47b9d5e1dd122d57ccd8bfbb3902612874c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1172007
Currently, host1x power refcount may decrement
to 0, while GPU is still powered on and we're still
servicing IRQs. So to prevent this situation,,
take a ref while GPU is being powered on, and
decrement it during power off. Since we are always
holding one reference while GPU is powered on,
we can remove this handling from gk20a_busy/idle().
Bug 200187507
Change-Id: Idabe88754f009f1e8de8dc821d53be3e013dc657
Signed-off-by: Sachit Kadle <skadle@nvidia.com>
Reviewed-on: http://git-master/r/1172320
(cherry picked from commit 3e27e6a5820f5c1ad05596553d75e8979b71f1bd)
Reviewed-on: http://git-master/r/1172607
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This reverts commit 6bbc169d33.
channel_suspend() might cause new interrupts to trigger,
and if irqs are already disabled, then these interrupts will
not get served
Hence revert this patch, and move disable_irq() to
original place
Bug 200207867
Change-Id: I45617a1a0aa9a1f805dd937a34ebb572a61c05c0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1169380
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
following compilation error are reported with CONFIG_DEBUG_FS=n:
pci.c:246:7: error: 'struct mm_gk20a' has no member named 'ltc_enabled'
pci.c:247:7: error: 'struct mm_gk20a' has no member named 'ltc_enabled_debug'
possible compilation error(reported sometime):
gk20a_allocator.c:1163:13: error: 'gk20a_alloc_debugfs_init' defined
but not used
fixed by adding '#ifdef CONFIG_DEBUG_FS' for debug only code.
following variables from gk20a.c are not initialized from
CONFIG_DEBUG_FS=n path, it will cause kernel oops when booting:
gk20a->mm.bypass_smmu = platform->bypass_smmu;
gk20a->mm.disable_bigpage = platform->disable_bigpage;
gk20a->mm.has_physical_mode = true;
fix it by move them out from '#ifdef CONFIG_DEBUG_FS' section.
Bug 1778001
Change-Id: Ic2da36b3f500882748ee46a5150903244b697761
Signed-off-by: David Pu <dpu@nvidia.com>
Reviewed-on: http://git-master/r/1167358
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Move all places that read ptimer to use the callback.
It's for add vgpu implementation of read ptimer.
Bug 1395833
Change-Id: Ia339f2f08d75ca4969a443fffc9a61cff1d3d2b7
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1159587
(cherry picked from commit a01f804684f875c9cffc31eb2c1038f2f29ec66f)
Reviewed-on: http://git-master/r/1158449
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
This reverts commit 2219f38727. It leaves
GPU in on state for some tests that require powering down GPU.
Change-Id: I79d44fed729e98692021c57bbeff6a0ef2e8c983
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1161846
We sometimes see race conditions where power refcount
is zero during ISR or bottom half.
If bottom half calls gk20a_busy(), it will lead to
boot up of GPU, but it is also possible that we are
already trying to poweroff GPU since power refcount
is zero
Fix this by taking a power refcount with gk20a_busy_noresume()
in ISR and then dropping this refcount at the end of
bottom half
Add new API gk20a_idle_nosuspend() to drop a refcount
without initiating suspend
Bug 200198908
Bug 1770522
Change-Id: Iec3d4dc8d468f49b71919d2bbc327da48b97bcab
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1160035
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
This CL covers the following modification,
1) Added multiple engine_info support
2) Added multiple runlist_info support
3) Initial changes for ASYNC CE support
4) Added ASYNC CE interrupt handling support
for gm206 GPU family
5) Added generic mechanism to identify the
CE engine pri_base address for gm206
(CE0, CE1 and CE2)
6) Removed hard coded engine_id logic and
made generic way
7) Code cleanup for readability
JIRA DNVGPU-26
Change-Id: I2c3846c40bcc8d10c2dfb225caa4105fc9123b65
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1155963
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Removed platform data parameter clockgate_delay, since it is not
really used for gpu clock gating any more. Also use railgate_delay
as autosuspend delay instead of clockgate_delay.
Change-Id: I5b594b5a0e84295ed9971ecdf4865dc1a7dd936d
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1159593
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
To be able to scan, PCI devnodes need to be in a directory with read
permission. By default /dev is read protected by SELinux policy. Move
the devnodes to their own directory so that reading this one
directory can be allowed.
At the same time rename the nodes to start with string "card-".
JIRA DNVGPU-54
Change-Id: I0df4ced08afd1f3a468e983d07395ffcb8050365
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1152745
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Add support for chips gm204 and gm206. Adds also support for reading
VBIOS and booting devinit and pre-os images on PMU.
Change-Id: I4824b44245611e5379ace62793cc37158048f432
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1120467
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ken Adams <kadams@nvidia.com>
Add below flag fields to gpu characteristics to indicate
supported and default preemption modes on platform for
graphics and compute
__u32 graphics_preemption_mode_flags;
__u32 compute_preemption_mode_flags;
__u32 default_graphics_preempt_mode;
__u32 default_compute_preempt_mode;
Add struct nvgpu_preemption_modes_rec to struct gr_gk20a
to store these values locally
Use platform specific get_preemption_mode_flags() to
get the flags and define gk20a/gm20b specific
get_preemption_mode_flags() API
Bug 1646259
Change-Id: I80193c0d988dc93bd96585f9aa631fd817f4dfa3
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1133595
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Deassert reset in L2 and FB before initializing L2. In gk20a L2 can
be off and thus writing registers results in a priv ring failure.
Change-Id: I680b8b1e77cf67a8269c6de59a15d9817301300e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1140482
(cherry picked from commit d85edcf4170d7bc59d2c080f4343bc2f959be023)
Reviewed-on: http://git-master/r/1143684
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
GPU characteristics hard coded GPC mask of 1 and returned number of
enabled GPCs as maximum number of GPCs. Fix both gpc_count and
max_gpc_count to be returned correctly.
JIRA DNVGPU-6
Change-Id: I41598b2f2d2ada26b0ad433f40a51e59b14deadd
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1142185
In gk20a_pm_shutdown(), we currently wait for 2s
for all channels to finish their work
But we already cancel all the nvgpu workers, freeze
user processes during shutdown
So the waiting should not be required, and hence
remove it
Bug 200166139
Change-Id: I0012f1b3c0f4f676958d083f8c60a001f7015fb0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1121918
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Fix below sparse warnings :
drivers/gpu/nvgpu/gk20a/gk20a.c:764:5: warning: symbol
'gk20a_pm_finalize_poweron' was not declared. Should it be static?
drivers/gpu/nvgpu/gk20a/channel_gk20a.c:2504:14:
warning: symbol 'gk20a_event_id_poll' was not declared. Should it be
static?
drivers/gpu/nvgpu/gk20a/channel_gk20a.c:2538:5:
warning: symbol 'gk20a_event_id_release' was not declared. Should it be
static?
Bug 200067946
Bug 200088648
Change-Id: I5c23e7ee09c1a18fe2eeff12f80a3c2bf73120ef
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1128060
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sri Krishna Chowdary <schowdary@nvidia.com>
gk20a_create_device now takes interface name as a parameter.
This patche adds it for ctxsw devnode.
Change-Id: Ic076159829574c6015056fb950f625a2233c015f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1123721
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Make necessary changes to support nvgpu on kernel-3.10
This includes below changes
- PROBE_PREFER_ASYNCHRONOUS is defined only for K3.10
- Fence handling and struct sync_fence is different between
K3.10 and K3.18
- variable status in struct sync_fence is atomic on K3.18
whereas it is int on K3.10
- if SOC == T132, set soc_name = "tegra13x"
- ioremap_cache() is not defined on K3.10 ARM versions,
hence use ioremap_cached()
Bug 200188753
Change-Id: I18d77eb1404e15054e8510d67c9a61c0f1883e2b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1121092
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Not all GPUs have stalling and non-stalling interrupt. Support
ones with just one interrupt line.
Change-Id: I0f1e8faa5b353b8d1b10691375bd853152379a3a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1120470
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Support GPUs which cannot choose between SMMU and physical
addressing.
Change-Id: If3256fa1bc795a84d039ad3aa63ebdccf5cc0afb
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1120469
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Use struct device instead of struct platform_device wherever
possible. This allows adding other bus types later.
Change-Id: I1657287a68d85a542cdbdd8a00d1902c3d6e00ed
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1120466
As a result GPU driver unfication, one instance of CONFIG_PM_RUNTIME
got introduced. So replacing it with CONFIG_PM.
Bug 200188753
Change-Id: If3f55ac32f6800c54e5bf620684b54b39457a6f4
Signed-off-by: Sumit Singh <sumsingh@nvidia.com>
Reviewed-on: http://git-master/r/1121650
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
As CONFIG_PM_GENERIC_DOMAINS_OF is disabled for l4t, so we have to
revert this cleanup, because removed portion of code is getting used
by l4t.
Bug 200188753
This reverts commit 25f0faeb37.
Change-Id: Ib9339b03d5ae55d11597690602802b6f723b7777
Signed-off-by: Sumit Singh <sumsingh@nvidia.com>
Reviewed-on: http://git-master/r/1121648
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
With NVGPU_IOCTL_CHANNEL_EVENTS_CTRL, nvgpu can
raise events to User space. But user space
cannot distinguish between various types of events.
To overcome this, we need finer-grained API to
deliver various events to user space.
Remove old API NVGPU_IOCTL_CHANNEL_EVENTS_CTRL,
and all the support for this API (we can remove
this since User space has not started using this
API at all)
Add new API NVGPU_IOCTL_CHANNEL_EVENT_ID_CTRL
which will accept an event_id (like BPT.INT or
BPT.PAUSE), a command to enable the event,
and return a file descriptor on which
we can raise the event (if cmd=enable)
Event is disabled when file descriptor is closed
Add file operations "gk20a_event_id_ops"
to support polling on event fd
Also add API gk20a_channel_get_event_data_from_id()
to get event_data of event from its id
Bug 200089620
Change-Id: I5288f19f38ff49448c46338c33b2a927c9e02254
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1030775
(cherry picked from commit 5721ce2735950440bedc2b86f851db08ed593275)
Reviewed-on: http://git-master/r/1120318
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
This change performs merge of 'PM_RUNTIME_Removal' dev-branch with
'dev-kernel-3.18' branch. It replaces CONFIG_PM_RUNTIME with CONFIG_PM.
JIRA TPM-704
Change-Id: I306e254716f275c283f727fc232d7244939542b6
Signed-off-by: Sumit Singh <sumsingh@nvidia.com>
Wait for 500 usec before ce reset to ensure that
no memory outstanding requests are pending.
Bug 1699365
Change-Id: I9f73f87cbbdca0208e95ebaee32dd1f764a3cd4f
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1116679
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Allow a special address space node to be split out from the
user adress space or fixed allocations. A debugfs node,
/d/<gpu>/separate_fixed_allocs
Controls this feature. To enable it:
# echo <SPLIT_ADDR> > /d/<gpu>/separate_fixed_allocs
Where <SPLIT_ADDR> is the address to do the split on in the
GVA address range. This will cause the split to be made in
all subsequent address space ranges that get created until it
is turned off. To turn this off just echo 0x0 into the same
debugfs node.
Change-Id: I21a3f051c635a90a6bfa8deae53a54db400876f9
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1030303
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
bug 1648908
This commit adds support for FECS ctxsw tracing. Code is compiled
conditionnaly under CONFIG_GK20_CTXSW_TRACE.
This feature requires an updated FECS ucode that writes one record to a ring
buffer on each context switch. On RM/Kernel side, the GPU driver reads records
from the master ring buffer and generates trace entries into a user-facing
VM ring buffer. For each record in the master ring buffer, RM/Kernel has
to retrieve the vmid+pid of the user process that submitted related work.
Features currently implemented:
- master ring buffer allocation
- debugfs to dump master ring buffer
- FECS record per context switch (with both current and new contexts)
- dedicated device for ctxsw tracing (access to VM ring buffer)
- SOF generation (and access to PTIMER)
- VM ring buffer allocation, and reconfiguration
- enable/disable tracing at user level
- event-based trace filtering
- context_ptr to vmid+pid mapping
- read system call for ctxsw dev
- mmap system call for ctxsw dev (direct access to VM ring buffer)
- poll system call for ctxsw dev
- save/restore register on ELPG/CG6
- separate user ring from FECS ring handling
Features requiring ucode changes:
- enable/disable tracing at FECS level
- actual busy time on engine (bug 1642354)
- master ring buffer threshold interrupt (P1)
- API for GPU to CPU timestamp conversion (P1)
- vmid/pid/uid based filtering (P1)
Change-Id: I8e39c648221ee0fa09d5df8524b03dca83fe24f3
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1022737
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reset controller is not enabled in all builds, so make its use
optional.
Change-Id: I88df11d0aae0552eb4c7f3acee5be70885ea2901
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1028348
Previously, only "high" priority bare channels were interleaved
between all other bare channels and TSGs. This patch decouples
priority from interleaving and introduces 3 levels for interleaving
a bare channel or TSG: high, medium, and low. The levels define
the number of times a channel or TSG will appear on a runlist (see
nvgpu.h for details).
By default, all bare channels and TSGs are set to interleave level
low. Userspace can then request the interleave level to be increased
via the CHANNEL_SET_RUNLIST_INTERLEAVE ioctl (TSG-specific ioctl will
be added later).
As timeslice settings will soon be coming from userspace, the default
timeslice for "high" priority channels has been restored.
JIRA VFND-1302
Bug 1729664
Change-Id: I178bc1cecda23f5002fec6d791e6dcaedfa05c0c
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/1014962
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
After commit b2b49ccbdd54 (PM: Kconfig: Set PM_RUNTIME if PM_SLEEP is
selected) PM_RUNTIME is always set if PM is set, so #ifdef blocks
depending on CONFIG_PM_RUNTIME may now be changed to depend on
CONFIG_PM.
Replace CONFIG_PM_RUNTIME with CONFIG_PM everywhere under
drivers/gpu/nvgpu/.
JIRA TPM-704
Change-Id: I23965838ff6ec77829076cd834e87641fb68e268
Signed-off-by: Sumit Singh <sumsingh@nvidia.com>
bug 200139995
Any GR register access should disable ELPG and clock gating before
access and enable it back after it is done. Disable ELPG while tweaking
perf parameters in gk20a_alloc_obj_ctx.
Also output NV_PBUS_INTR_0 in case of interrupt (including fix to
display correct value on pbus isr).
Change-Id: I81d2eb4461e92fbb33db8554779f6566f6b002c1
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/835307
(cherry picked from commit 6acc35bd1bcc706fbde8d11521cf1d0f64a16fe4)
Reviewed-on: http://git-master/r/921299
(cherry picked from commit 73afd520445bb1f4757fd167b38289143fd46d80)
Reviewed-on: http://git-master/r/930040
(cherry picked from commit 7a784ebea0dd60a88469f51eaa61c33b356e499c)
Reviewed-on: http://git-master/r/1023529
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
