Commit Graph

7 Commits

Author SHA1 Message Date
Sagar Kamble
57f3968cb9 gpu: nvgpu: mc: address code inspection gaps
Address following issues uncovered during inspection:
1. Remove the doxygen comment from nvgpu_wait_for_deferred_interrupts
   definition.
2. Use NVGPU_MC_INTR_STALLING instead of hardcoding the index.
3. Define doxygen groups NVGPU_MC_UNIT_ENUMS,
   NVGPU_MC_INTR_TYPE_DEFINES, NVGPU_MC_INTR_UNIT_DEFINES and
   NVGPU_MC_INTR_ENABLE_DEFINES.
4. Update the doxygen comments.
5. Fix the cleanup, typo in the description of the test
   test_wait_for_deferred_interrupts.

JIRA NVGPU-4795

Change-Id: Ifc6756832aabf9dd42ee174eb1373495e6d38c86
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2287627
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2020-12-15 14:13:28 -06:00
Sagar Kamble
ad6a1b141f gpu: nvgpu: remove unneeded headers inclusion
Remove the header inclusions that are not needed in falcon and mc
units.

JIRA NVGPU-4795
JIRA NVGPU-4787

Change-Id: I39f639b01f321b7b4e969d839daef8efe22617e9
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2287718
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2020-12-15 14:13:28 -06:00
Thomas Fleury
6fa5da61d7 gpu: nvgpu: use engine_id to access engine_info
Generalize use of "engine_id" variable name to index f->engine_info.

Jira NVGPU-4511

Change-Id: Ie3bc2c701dc3bab833d6ac134273dd6a102528c2
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2262219
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
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2020-12-15 14:10:29 -06:00
Sagar Kamble
a8c9c800cd gpu: nvgpu: reorganization of MC interrupts control
Previously, unit interrupt enabling/disabling and corresponding MC level
interrupt enabling/disabling was not done at the same time.
With this change, stall and nonstall interrupt for units are programmed
at MC level along with individual unit interrupts. Kept access to MC
interrupt registers through mc.intr_lock spinlock.

For doing this separated CE and GR interrupt mask functions.
mc.intr_enable is only used when there is global interrupt
control to be set. Removed mc_gp10b.c as mc_gp10b_intr_enable
is now removed. Removed following functions - mc_gv100_intr_enable,
mc_gv11b_intr_enable & intr_tu104_enable. Removed intr_pmu_unit_config
as we can use the generic unit interrupt control function.

JIRA NVGPU-4336

Change-Id: Ibd296d4a60fda6ba930f18f518ee56ab3f9dacad
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196178
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2020-12-15 14:10:29 -06:00
Sagar Kamble
f2b49f1c40 gpu: nvgpu: add doxygen for common MC unit
Add doxygen details about Master Control (MC) common unit. Moved the
interrupt handling related variables to new structure nvgpu_mc.

JIRA NVGPU-2524

Change-Id: I61fb4ba325d9bd71e9505af01cd5a82e4e205833
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2226019
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2020-12-15 14:10:29 -06:00
Philip Elcan
065f98f669 gpu: nvgpu: init: add return for all init APIs
This adds return values for all init APIs. This make all the init APIs
have the same signature. This is a prerequisite to making a table of
init functions.

JIRA NVGPU-3980

Change-Id: I5b71fd06ad248092af133ffe908e2930acb6d2b0
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202973
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2020-12-15 14:05:52 -06:00
Debarshi Dutta
69ef86e627 gpu: nvgpu: move safe code HAL files to fusa
This patch moves all the safe static and non-static functions as well
as its dependencies such as static declared structs into files with
_fusa.c extension. If the original file is left with no functions
remaining then the file is deleted.

Added changes in Makefile, Makefile.sources, nvgpu-hal-new.yaml for
compilation.

Jira NVGPU-3690

Change-Id: I81af67c308705faf8a681df63a6778e7de2076cf
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2146761
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2019-07-03 02:46:15 -07:00