Commit Graph

75 Commits

Author SHA1 Message Date
Abdul Salam
6945209418 gpu: nvgpu: Add unified check for clk_arb support
Currently clk_arb needs PSTATE to be true for dGPU.
Setting PSTATE only FALSE, causes issue as clk_arb fails.
There is no such dependency of PSTATE on iGPU.
Making it unified with a call to check_clk_arb_support().
This call is implemented based on its dependency in iGPU, dGPU.
check_clk_arb_support returns true if supported, else false.

Jira NVGPU-1948

Change-Id: I108dc12bd6ad8d0e074352080c978b7dda9bee05
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2014775
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2019-02-12 08:54:49 -08:00
Philip Elcan
2beed190a7 gpu: nvgpu: clk: update type for size param
Update interfaces to use size_t to align with boardobj_construct_super()
and avoid unnecessary casts.

JIRA NVGPU-1008

Change-Id: Ib4539239363f106f1fba8d523072b28d0b8369ad
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011434
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Scott Long <scottl@nvidia.com>
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Reviewed-by: Adeel Raza <araza@nvidia.com>
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2019-02-11 14:04:25 -08:00
Mahantesh Kumbar
9dda177510 gpu: nvgpu: use common BOARDOBJGRP SET/GET_STATUS construct
Currently there are multiple BOARDOBJGRP SET/GET_STATUS construct
added to support for 3.5 pstate, _pack boardobjs & to fetch respective
offset/size of boardobjs from PMU super surface.
With super surface member descriptor(SSMD) support, boardobj offset
will be part of SSMD lookup table which is part of PMU super surface
buffer & updated by PMU RTOS during init stage,
So, making changes to use common BOARDOBJGRP SET/GET_STATUS
construct define which fetchs offset/size from SSMD,
& deleting other BOARDOBJGRP construct defines.

JIRA NVGPU-1874

Change-Id: I4e3d9ad31da33a836c5e9219321c68d867c2a172
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2000860
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2019-02-07 04:15:31 -08:00
Abdul Salam
59b93d1572 gpu: nvgpu: Add exit condition in clk_arb wq.
Currently clk_arb wq waits only for tasks.
Sometimes this doesnt invoke wq when thread_stop is called.
Add a check for thread_stop when waiting in wq.
Remove atomic_inc when no job is submitted.
Use current_time_ns() instead of ptimer to get time.

Bug 200488054

Change-Id: I770d566dd29371bd189d30dd5e60a6b23a9c98ff
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2012244
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2019-02-06 03:45:59 -08:00
Adeel Raza
d828e013db gpu: nvgpu: common: MISRA rule 15.6 fixes
MISRA rule 15.6 requires that all if/else/loop blocks should be enclosed
by brackets. This patch adds brackets to single line if/else/loop blocks
in the common directory.

JIRA NVGPU-775

Change-Id: I0dfb38dbf256d49bc0391d889d9fbe5e21da5641
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011655
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Scott Long <scottl@nvidia.com>
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-02-05 19:23:47 -08:00
Philip Elcan
75e4e7c9bc gpu: nvgpu: clk: address MISRA 10.3 violations
This fixes a number of miscellaneous MISRA 10.3 violations in
common/pmu/clk/ for assignment of objects of different size or essential
type.

JIRA NVGPU-1008

Change-Id: If93aa9fc4f0f49ea678e39111f323ef4d53f5ec5
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2008771
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2019-02-01 13:45:22 -08:00
Philip Elcan
182aadfd71 gpu: nvgpu: clk: fix MISRA 10.3 issues in clk_arb
MISRA Rule 10.3 prohibits direct assignment of an object of different
essential type or narrower type. This change addresses a number of
miscellaneous violations in clk_arb.

JIRA NVGPU-1008

Change-Id: Iac21ee0c658d55b0c9f7b2d8ea0e134d6fc3c6c5
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2001231
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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2019-01-31 11:05:00 -08:00
Philip Elcan
a2ce1dfd37 gpu: nvgpu: clk: casts for atomic ops in clk_arb
Add the appropriate casts for the atomic ops in clk_arb.c to eliminate a
number of MISRA 10.3 violations.

JIRA NVGPU-1008

Change-Id: Ie098969584734f366901f8b2aaf1e2788fc18753
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2001230
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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2019-01-31 11:04:56 -08:00
Philip Elcan
65c20fe411 gpu: nvgpu: clk: pass u32 for event number
Change the type of the event_number parameter of
nvgpu_clk_notification_queue_alloc() from size_t to u32 since it's
used everywhere as a u32.

JIRA NVGPU-1008

Change-Id: I4305a3816a55a9f5c91439e141d0811bd1b422e8
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2001229
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Abdul Salam <absalam@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-01-31 11:04:52 -08:00
Philip Elcan
b502e5405a gpu: nvgpu: clk: return u32 for pstate
Change the return type for the HAL API get_current_pstate() from int to
u32 since that's the real type of the pstate and how the callers are
using it.

JIRA NVGPU-1008

Change-Id: Idc6d458212045ceaab724500976cb41d5b1ffc39
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2001228
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2019-01-31 11:04:49 -08:00
Abdul Salam
e2a29dbb96 gpu: nvgpu: Align the nvrm freq to match latest VF point
In the below scenario
1. nvrm app requests & gets all VF points from nvgpu.
2. nvrm stores all the VF points and starts setting each point.
3. During step 2, VF gets updated in nvgpu due to some events.
4. There is a mismatch b/w points in nvrm and VF table in nvgpu.
5. If nvrm freq is less than nvgpu freq , PMU cant program.
Makesure highest between nvrm and VF table goes to PMU

Bug 200454682

Change-Id: I9c58f129ff1c0dfb3f4759242469b3622fe11bb2
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2000238
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2019-01-30 10:06:22 -08:00
Vaibhav Kachore
3c55163713 Revert "Revert "gpu: nvgpu: Reading Vmin and Volt_rail get status""
This reverts commit dcd4673e38.

Bug 2487534

Change-Id: I855e610b8fa46c12ca52c16edc247e5bbe9908b6
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2003914
Reviewed-by: Pekka Pessi <ppessi@nvidia.com>
Tested-by: Pekka Pessi <ppessi@nvidia.com>
2019-01-29 07:55:43 -08:00
Vaibhav Kachore
f13b5d90e3 Revert "Revert "gpu: nvgpu: Add quantization to slave VF Points""
This reverts commit 8f3bf00b5a.

Bug 2487534

Change-Id: I6d2ce7229adf010080b4a04386c449f2433fedae
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2003915
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Ranjanikar Nikhil Prabhakarrao <rprabhakarra@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
2019-01-29 07:53:59 -08:00
Vaibhav Kachore
dcd4673e38 Revert "gpu: nvgpu: Reading Vmin and Volt_rail get status"
This reverts commit f048bb5a71.

Bug 2487534

Change-Id: Ie96351b09e658d8e4c0307c8f73a524e9c532ee7
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2003148
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Tested-by: Konsta Holtta <kholtta@nvidia.com>
2019-01-25 00:49:50 -08:00
Vaibhav Kachore
8f3bf00b5a Revert "gpu: nvgpu: Add quantization to slave VF Points"
This reverts commit c57cf00aa0.

Bug 2487534

Change-Id: I094d88487accf0be7ed1c050941a20ffccc1df35
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2003147
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Tested-by: Konsta Holtta <kholtta@nvidia.com>
2019-01-25 00:49:24 -08:00
Philip Elcan
69d975fcbc gpu: nvgpu: clk: fix MISRA 10.3 issue in clk_prog
MISRA Rule 10.3 prohibits implicit assignment of an object from a
different size type. This fixes a MISRA 10.3 violation for assigning a
u16 to a u8 in clk_prog.c.

JIRA NVGPU-1008

Change-Id: I565a4aba62dac30943d9c9d012ca0a0d6a256578
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2001227
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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2019-01-23 13:55:23 -08:00
Philip Elcan
fea84c09fa gpu: nvgpu: clk: fix MISRA 10.3 issues for size_t
MISRA Rule 10.3 prohibits implicit casting of objects to a different
type. This change addresses a number of MISRA 10.3 violations in
clk_prog.c where size_t values were being implicitly cast to u16.

JIRA NVGPU-1008

Change-Id: I39a257a056faf0f903363ed8d697efa88d74e75e
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2001226
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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2019-01-23 13:55:19 -08:00
Philip Elcan
76acbc02bc gpu: nvgpu: clk: fix return type for vflookup()
This changes the return type for the API fvlookup() from a u32 to an
int. The implementation of the API in vflookup_prob_1x_master() was
already trying to return negative values. This allows users of the API
to properly check the return value.

JIRA NVGPU-1008

Change-Id: Ifb12b5ffbde7fed501e7dfec9bd6a28dcc1b242e
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2001225
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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2019-01-23 13:55:15 -08:00
Philip Elcan
99ed40b7fb gpu: nvgpu: clk: fix MISRA 10.3 issues for size_t
MISRA Rule 10.3 prohibits implicit casting of objects to a different
type. This change addresses a number of MISRA 10.3 violations in
clk_domain.c where size_t values were being implicitly cast to u16.

JIRA NVGPU-1008

Change-Id: If2dc6c6a288fe4b16425a210bc6d76bbef2ce019
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2001224
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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2019-01-23 13:55:12 -08:00
Philip Elcan
2cff6844fb gpu: nvgpu: clk: use explicit BIT32 macro
Use the BIT32() macro to create 32 bit values when assigning to a u32.
This avoids MISRA 10.3 violations for assigning different types to a
u32.

JIRA NVGPU-1008

Change-Id: I0b50c3cf476737d38c943ecc12c4f17f9ba9ddb8
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2001223
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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2019-01-23 13:55:08 -08:00
Philip Elcan
968db82a65 gpu: nvgpu: clk: fix incorrect casts in returns
Remove the u32 casting for return values in functions whose return type
is int.

JIRA NVGPU-1008

Change-Id: I87d4e3a4f8530f45b59a1f612180b295c5238b28
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2001222
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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2019-01-23 13:55:04 -08:00
rmylavarapu
f048bb5a71 gpu: nvgpu: Reading Vmin and Volt_rail get status
Changes:
1) volt_rail_boardobj_grp_get_status function implemented.
2) nvgpu_volt_get_vmin_tu10x function implemented.
3) Only Vmin is updated into boardobjs.

Bug 200454682
Bug 2481917

Change-Id: Ie070b28a78503eeb3003493b5f130a4dcd9b1275
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1996137
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2019-01-17 09:15:22 -08:00
Abdul Salam
c57cf00aa0 gpu: nvgpu: Add quantization to slave VF Points
All slave clock should be quantized as per step size.
TU104 has 15Mhz as step size.
Enable clk_arb without enabling clk_freq_controller.
clk_freq_controller is not needed for Auto use case.
Increase the maxclk only when master is less that slave clock.
This is needed when gpcclk is less than slave P0 min.
Use get_status to get Vim and use it for change sequencer.
Add support for Device Events

Bug 200454682
Bug 2481917

Change-Id: Ie0c404f4b77e41f6a1719b52d6e29a5ac757b41b
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1994831
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2019-01-17 09:15:19 -08:00
Scott Long
0837b6988c gpu: nvgpu: container_of() changes to clk arb code
The container_of() macro used in nvgpu produces the following
set of MISRA required rule violations:

 * Rule 11.3 : A cast shall not be performed between a pointer to
               object type and a pointer to a different object type.
 * Rule 11.8 : A cast shall not remove any const or volatile
               qualification from the type pointed to be a pointer.
 * Rule 20.7 : Expressions resulting from the expansion of macro
               parameters shall be enclosed in parentheses.

Using the same modified implementation of container_of() as that
used in the nvgpu_list_node/nvgpu_rbtree_node routines eliminates
the Rule 11.8 and Rule 20.7 violations and exchanges the Rule 11.3
violation with an advisory Rule 11.4 violation.

This patch uses that same equivalent implementation in two new
(static) functions that are used to replace references to
container_of() references in clk arb code:

 * nvgpu_clk_dev_from_refcount
 * nvgpu_clk_session_from_refcount

It should be noted that replacement functions still contain
potentially dangerous (and non-MISRA compliant code) and that it is
expected that deviation requests will be filed for the new advisory
rule violations accordingly.

JIRA NVGPU-782

Change-Id: I612990e9c27f10d0ce3ac76729529aa1eb15d42a
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1993796
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-01-14 20:34:26 -08:00
Terje Bergstrom
dce78f7332 gpu: nvgpu: Move PMU code to common/pmu
Move code interfacing with PMU tasks to common/pmu.

JIRA NVGPU-961

Change-Id: Ie62611b0ffe1196d4bfdc740e03017e1894a834f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1950991
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2019-01-10 20:09:55 -08:00