Commit Graph

15 Commits

Author SHA1 Message Date
Rajesh Devaraj
935c5f6578 gpu: nvgpu: fix misra violations in SDL
This patch addresses misra violations due to SDL error reporting
callbacks. In particular, it addresses the following misra violation:

- misra_c_2012_directive_4_7_violation: Calling function
  "nvgpu_report_*_err()" which returns error information without testing
  the error information.

JIRA NVGPU-4025

Change-Id: Ia10b6b3fd9c127a8c5189c3b6ba316f243cedf04
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196895
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2020-12-15 14:05:52 -06:00
Seshendra Gadagottu
07b86032ef gpu: nvgpu: reduce code complexity in ltc intr unit
Reduced code complexity for gv11b_ltc_intr_handle_rstg_ecc_interrupts function
from 19 to 7 using following helper functions:
gv11b_ltc_intr_init_counters: code complexity 5
gv11b_ltc_intr_handle_rstg_ecc_interrupts: code complexity 3
gv11b_ltc_intr_handle_tstg_ecc_interrupts: code complexity 3
gv11b_ltc_intr_handle_dstg_ecc_interrupts: code complexity 5

JIRA NVGPU-3976

Change-Id: Iad3aad58c28255629087ecba943118f040cdbbd5
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2192091
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2020-12-15 14:05:52 -06:00
Adeel Raza
252ddc4f05 gpu: nvgpu: add coverity whitelisting support
Add macros for whitelisting coverity violations. These macros use pragma
directives. The pragma directives and whitelisting macros are only
enabled when a coverity scan is being run.

The whitelisting macros have been added to a new header called
static_analysis.h. The contents of safe_ops.h (CERT C safe ops) have
been moved into static_analysis.h because this will be the new header
for static analysis related macros/defines/etc.

JIRA NVGPU-3820

Change-Id: I9c63f20f670880b420415535738034619314b7c3
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2180600
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2020-12-15 14:05:52 -06:00
Rajesh Devaraj
2272e04861 gpu: nvgpu: add description for tpc id and slice id checks
This patch adds description to emphasize the necessity to do the
maximum value check for TPC and SLICE IDs.

JIRA NVGPU-3867

Change-Id: I69029bb3b3888590b5a1d1869058e9ae125775bb
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2183875
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-08-27 00:08:05 -07:00
Seshendra Gadagottu
d5d31e5b17 gpu: nvnpu: ltc: fix misra-c rule 8.6 violations
Fix rule 8.6 misra violation in ltc code by enclosing
following functions defs under CONFIG_NVGPU_FALCON_NON_FUSA
switch.

gp10b_ltc_intr_configure
gp10b_ltc_intr_isr
gm20b_determine_L2_size_bytes
gm20b_ltc_set_enabled
gm20b_ltc_init_fs_state

Added following functions defs under CONFIG_NVGPU_INJECT_HWERR
switch.

gv11b_ltc_get_err_desc
gv11b_ltc_inject_ecc_error

Also added hal initializations under relevant switch.

JIRA NVGPU-3872

Change-Id: I6800ae4a8fcd91e534df97e8db7770f0e4e9112a
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2174827
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-08-27 00:06:37 -07:00
Rajesh Devaraj
8009a4f8c8 gpu: nvgpu: check slice and tpc id
This patch adds the check to validate the slice id and tpc id before
packing them along with ltc id and gpc id, respectively.

JIRA NVGPU-3867

Change-Id: I01cf095327ecc9c567c2d074ef1daa944377d15f
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2180374
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-08-22 00:37:30 -07:00
Debarshi Dutta
69ef86e627 gpu: nvgpu: move safe code HAL files to fusa
This patch moves all the safe static and non-static functions as well
as its dependencies such as static declared structs into files with
_fusa.c extension. If the original file is left with no functions
remaining then the file is deleted.

Added changes in Makefile, Makefile.sources, nvgpu-hal-new.yaml for
compilation.

Jira NVGPU-3690

Change-Id: I81af67c308705faf8a681df63a6778e7de2076cf
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2146761
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-07-03 02:46:15 -07:00
Seshendra Gadagottu
344eceb739 gpu: nvgpu: fix CERT-C issues in ltc intr driver
Use nvgpu_safe_add_u32 for u32 additions in ltc interrupt
driver.

JIRA NVGPU-3623

Change-Id: If4d1b126836c5980e7016ed42b588b435f4f7f66
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2135322
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-06-13 13:15:27 -07:00
Seshendra Gadagottu
bf68ff68f0 gpu: nvgpu: fix CERT-C errors in hal.ltc.intr driver
Fixed CERT-C issues in hal ltc intr driver by replacing
arithmetic operations with nvgpu safe ops.

JIRA NVGPU-3623

Change-Id: I80c3dd9e42dd20bb853db6e60d6a1fd36415ab36
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2134686
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-06-12 05:08:29 -07:00
Alex Waterman
9d00bea358 Revert "gpu: nvgpu: fix CERT-C errors in hal.ltc.intr driver"
This reverts commit bf861813b7.

This seems to cause a unit test failure in GVS due to a missing channel
test run.

Change-Id: I8609ebf8862a9641b015a7a2c0693e58312ef31d
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2134477
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
2019-06-11 10:50:00 -07:00
Seshendra Gadagottu
bf861813b7 gpu: nvgpu: fix CERT-C errors in hal.ltc.intr driver
Fixed CERT-C issues in hal ltc intr driver by replacing
arithmetic operations with nvgpu safe ops.

JIRA NVGPU-3623

Change-Id: I4203e7bdd02c41578cad8446f02247749c8cef5c
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2133291
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-06-11 03:55:33 -07:00
Rajesh Devaraj
05ed37ae3a gpu: nvgpu: remove usage of hw headers from SDL
This patch does the following:
(1) Removes the usage of hw headers in SDL unit. For this purpose, it moves
    the initialization required for errors that can be injected using hw
    support, error injection function. Further, it passes the required
    information to SDL via hal layers.
(2) Renames (i) PWR as PMU, (ii) nvgpu_report_ecc_parity_err to
    nvgpu_report_ecc_err.

Jira NVGPU-3235

Change-Id: I69290af78c09fbb5b792058e7bc6cc8b6ba340c9
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2112837
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-31 04:06:51 -07:00
Rajesh Devaraj
fcb7635a92 gpu: nvgpu: gops initialization for SDL
This patch moves gops init related to SDL from qnx to common-core. For this
purpose, it does the following changes:
- Adds stub functions for linux and posix.
- Updates nvgpu_init.c for mapping err_ops with report error APIs.
- Updates nvgpu_err.h header file to include prototypes related to error
  reporting APIs.
- Updates nvgpu-linux.yaml file to include sdl_stub file.

Jira NVGPU-3237

Change-Id: Idbdbe6f8437bf53504b29dc2d50214484ad18d6f
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119681
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-30 02:18:05 -07:00
Alex Waterman
3a764030b1 gpu: nvgpu: Add new mm HAL and move cache code to that HAL
Add a new MM HAL directory to contain all MM related HAL units.
As part of this change add cache unit to the MM HAL. This contains
several related fixes:

1. Move the cache code in gk20a/mm_gk20a.c and gv11b/mm_gv11b.c to
   the new cache HAL. Update makefiles and header includes to take
   this into account. Also rename gk20a_{read,write}l() to their
   nvgpu_ variants.

2. Update the MM gops: move the cache related functions to the new
   cache HAL and update all calls to this HAL to reflect the new
   name.

3. Update some direct calls to gk20a MM cache ops to pass through
   the HAL instead.

4. Update the unit tests for various MM related things to use the
   new MM HAL locations.

This change accomplishes two architecture design goals. Firstly it
removes a multiple HW include from mm_gk20a.c (the flush HW header).
Secondly it moves code from the gk20a/ and gv11b/ directories into
more proper locations under hal/.

JIRA NVGPU-2042

Change-Id: I91e4bdca4341be4dbb46fabd72622b917769f4a6
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2095749
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-16 17:06:42 -07:00
Seshendra Gadagottu
9346b104d4 gpu: nvgpu: ltc: create sub-unit for ltc intr
Created sub-unit for ltc interrupt handling.
Following 2-hals are moved from ltc to ltc intr unit:
void (*isr)(struct gk20a *g, u32 ltc);
void (*en_illegal_compstat)(struct gk20a *g, bool enable)

Added new hal in ltc intr sub-unit for configuring ltc interrupts:
void (*configure)(struct gk20a *g);

Moved ltc interrupt related code from ltc to ltc intr unit.
Chip ltc.intr hals are populated with updated function names
created in ltc intr unit.

Converted all "unsigned int" usage to "u32" in ltc and ltc intr units
to match with hardware 32 bit register read/write.

JIRA NVGPU-3042
JIRA NVGPU-2044

Change-Id: I8684dfcc8ae343e4588b93f2b0ccde0e227635df
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081140
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-03-27 10:26:02 -07:00