Commit Graph

22 Commits

Author SHA1 Message Date
Philip Elcan
06fd513e1e gpu: nvgpu: move common.unit into common.mc
nvgpu.common.unit was just an enum used for passing to nvgpu.common.mc
APIs. So, move the enum into mc.h, and replace the include of unit.h
with mc.h where appropriate. And update the yaml arch.

JIRA NVGPU-4144

Change-Id: I210ea4d3b49cd494e43add1b52f3fbcdb020a1e3
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2216106
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2020-12-15 14:10:29 -06:00
Sagar Kamble
3444d729fd gpu: nvgpu: update compiling out cg changes
nvgpu_cg_pg_enable|disable functions are non-safe hence compile out
power_features.c. Corresponding functions from cg.c are also not
compiled. for e.g. nvgpu_cg_elcg_enable|disable, nvgpu_cg_blcg-
_mode_enable|disable, nvgpu_cg_slcg_gr_perf_ltc_load_enable|disable,
nvgpu_cg_elcg_set_elcg|blcg|slcg_enabled.
BLCG handling in nvgpu_cg_set_mode is non-safe hence compile it out
as well.

JIRA NVGPU-2175

Change-Id: I9940cc418d84eb30979dd50a2ed4a132473312fe
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2168957
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2020-12-15 14:05:52 -06:00
Thomas Fleury
9836420185 gpu: nvgpu: no engine reset when recovery is disabled
Compile out nvgpu_engine_reset and nvgpu_gr_reset when
CONFIG_NVGPU_RECOVERY is not defined.

Jira NVGPU-3886

Change-Id: I7ff67cf3680dfff2130e2a9e16d68b5a3f684bd4
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2175430
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2019-08-15 13:26:09 -07:00
Thomas Fleury
c7b41f106d gpu: nvgpu: add CONFIG_NVGPU_RECOVERY
Add CONFIG_NVGPU_RECOVERY in order to conditionally compile
recovery code. This code will be removed from safety build
when sw quiesce state is implemented, and negative tests are
disabled or modified such that they do not expect recovery
to happen.

Added static inline functions for recovery handlers, when
CONFIG_NVGPU_RECOVERY is not defined. These inline functions
can later be wired to the sw quiesce functions.

Also moved gv11b recovery code to non-fusa, as it will ultimately
be removed from safety build.

Jira NVGPU-3871

Change-Id: Ia705b059fab6120899c7e15082f2a0f51ff51dc9
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2166074
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2019-08-07 08:25:57 -07:00
Debarshi Dutta
69ef86e627 gpu: nvgpu: move safe code HAL files to fusa
This patch moves all the safe static and non-static functions as well
as its dependencies such as static declared structs into files with
_fusa.c extension. If the original file is left with no functions
remaining then the file is deleted.

Added changes in Makefile, Makefile.sources, nvgpu-hal-new.yaml for
compilation.

Jira NVGPU-3690

Change-Id: I81af67c308705faf8a681df63a6778e7de2076cf
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2146761
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2019-07-03 02:46:15 -07:00
Thomas Fleury
c2eb26436a gpu: nvgpu: Add doxygen documentation in runlist.h
Removed the following unused fields from runlist context:
- total_entries
- stopped
- support_tsg

Renamed:
- nvgpu_fifo_runlist_set_state -> nvgpu_runlist_set_state

Removed RUNLIST_INVALID_ID which was redundant with
NVGPU_INVALID_RUNLIST_ID.

Jira NVGPU-3594

Change-Id: I23d1abdf87b73bc0138816dab6659249f2602b9f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2139520
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-06-24 17:36:29 -07:00
Sagar Kamble
3f08cf8a48 gpu: nvgpu: rename feature Make and C flags
Name the Make and C flag variables consistently wih syntax:
CONFIG_NVGPU_<feature name>

s/NVGPU_DEBUGGER/CONFIG_NVGPU_DEBUGGER
s/NVGPU_CYCLESTATS/CONFIG_NVGPU_CYCLESTATS
s/NVGPU_USERD/CONFIG_NVGPU_USERD
s/NVGPU_CHANNEL_WDT/CONFIG_NVGPU_CHANNEL_WDT
s/NVGPU_FEATURE_CE/CONFIG_NVGPU_CE
s/NVGPU_GRAPHICS/CONFIG_NVGPU_GRAPHICS
s/NVGPU_ENGINE/CONFIG_NVGPU_FIFO_ENGINE_ACTIVITY
s/NVGPU_FEATURE_CHANNEL_TSG_SCHED/CONFIG_NVGPU_CHANNEL_TSG_SCHED
s/NVGPU_FEATURE_CHANNEL_TSG_CONTROL/CONFIG_NVGPU_CHANNEL_TSG_CONTROL
s/NVGPU_FEATURE_ENGINE_QUEUE/CONFIG_NVGPU_ENGINE_QUEUE
s/GK20A_CTXSW_TRACE/CONFIG_NVGPU_FECS_TRACE
s/IGPU_VIRT_SUPPORT/CONFIG_NVGPU_IGPU_VIRT
s/CONFIG_TEGRA_NVLINK/CONFIG_NVGPU_NVLINK
s/NVGPU_DGPU_SUPPORT/CONFIG_NVGPU_DGPU
s/NVGPU_VPR/CONFIG_NVGPU_VPR
s/NVGPU_REPLAYABLE_FAULT/CONFIG_NVGPU_REPLAYABLE_FAULT
s/NVGPU_FEATURE_LS_PMU/CONFIG_NVGPU_LS_PMU
s/NVGPU_FEATURE_POWER_PG/CONFIG_NVGPU_POWER_PG

JIRA NVGPU-3624

Change-Id: I8b2492b085095fc6ee95926d8f8c3929702a1773
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130290
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2019-06-11 09:46:24 -07:00
Deepak Nibade
649a2b57a8 gpu: nvgpu: add debugger flag for hal.gr.gr unit
Add NVGPU_DEBUGGER flag for common.hal.gr.gr unit and corresponding
hals.

Also add this flag for deferred reset functionality

Jira NVGPU-3506

Change-Id: Iee4fbc1305346bb4d779cd69e8fd5539cb07206b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130149
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2019-06-06 16:28:44 -07:00
Mahantesh Kumbar
b691df5a02 gpu: nvgpu: compile out PMU members & headers for safety
-compile out nvgpu_pmu members which are not required for
safety buid & modified source as required to support same.
-compile out PMU headers include which are not required for
safety code
-Removed unnecessary PMU header includes from some files

JIRA NVGPU-3418

Change-Id: I5364b1b16c46637d229e82745dd2846cb6335a72
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128228
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2019-06-06 06:55:58 -07:00
Mahantesh Kumbar
90aee0086f gpu: nvgpu: rename NVGPU_LS_PMU to NVGPU_FEATURE_LS_PMU
renamed NVGPU_LS_PMU to NVGPU_FEATURE_LS_PMU to follow
nvgpu naming standard
Compile out LS PMU files when PMU RTOS support is
disabled for safety build by setting NVGPU_LS_PMU
build flag to 0

JIRA NVGPU-3418

Change-Id: Ib09924ac25657e932723c10be573f2f701cb7bea
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127794
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2019-05-30 19:27:14 -07:00
Mahantesh Kumbar
120defb7cb gpu: nvgpu: compile out PMU mutex code for safety
Compile out PMU mutex calls called from other unit when
PMU RTOS support is disabled for safety build by setting
NVGPU_LS_PMU build flag to 0

NVGPU JIRA-3418

Change-Id: I040a744d5102f7fd889d4e8ad6e94129eadb73dd
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2124698
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2019-05-30 19:25:42 -07:00
Mahantesh Kumbar
3d1169544f gpu: nvgpu: alloc space for PMU's struct nvgpu_pmu at runtime
Allocating space for struct nvgpu_pmu at run time as part of
nvgpu_pmu_early_init() stage and made required changes to
dependent fiels as needed.

JIRA NVGPU-1972

Change-Id: I2d1c86d713e533c256ba95b730aa2e9543a66438
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110109
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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2019-05-23 00:56:55 -07:00
Mahantesh Kumbar
0a64f6cb2d gpu: nvgpu: PMU pmu.c/h header include cleanup
Some headers are not required to include in pmu.c/h as
lot of PMU code restructure happened, so removed headers
which not required anymore.

JIRA NVGPU-1972

Change-Id: Iead7f049d167cdaaaf7c75c2a5e19ae7b068fe6b
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110108
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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2019-05-23 00:56:45 -07:00
Debarshi Dutta
17486ec1f6 gpu: nvgpu: rename tsg_gk20a and channel_gk20a structs
rename struct tsg_gk20a to struct nvgpu_tsg and rename struct
channel_gk20a to struct nvgpu_channel

Jira NVGPU-3248

Change-Id: I2a227347d249f9eea59223d82f09eae23dfc1306
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2112424
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2019-05-06 02:56:53 -07:00
Seema Khowala
cfb4ff0bfb gpu: nvgpu: rename struct fifo_gk20a
Rename
struct fifo_gk20a -> nvgpu_fifo

JIRA NVGPU-2012

Change-Id: Ifb5854592c88894ecd830da092ada27c7f05380d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109625
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Reviewed-by: Adeel Raza <araza@nvidia.com>
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2019-05-03 16:25:43 -07:00
Seema Khowala
170d7464d6 gpu: nvgpu: move fifo_gk20a.[ch] to hal/fifo
Move fifo_gk20a struct to fifo.h
Move fifo_gk20a.[ch] to hal/fifo

Add missing includes for fifo subunits.

JIRA NVGPU-2012

Change-Id: I8bf5402bd5a9f8ff9f6a818cee553b57e117f3bc
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109012
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2019-05-02 23:40:42 -07:00
Seema Khowala
39070c653f gpu: nvgpu: move FIFO_INVAL_* out of fifo_gk20a.h
Move and rename
FIFO_INVAL_ENGINE_ID -> NVGPU_INVALID_ENG_ID
FIFO_INVAL_TSG_ID -> NVGPU_INVALID_TSG_ID
FIFO_INVAL_RUNLIST_ID -> NVGPU_INVALID_RUNLIST_ID
FIFO_INVAL_SYNCPT_ID -> NVGPU_INVALID_SYNCPT_ID
FIFO_INVAL_CHANNEL_ID -> NVGPU_INVALID_CHANNEL_ID

JIRA NVGPU-2012

Change-Id: Ic4cc16ece64d85e22f16e4d28dcfd0c187bb65f3
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109011
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2019-05-02 23:40:26 -07:00
Seema Khowala
3392a72d1a gpu: nvgpu: move runlist related struct and defines
Move from fifo_gk20a.h to runlist.h
RUNLIST_DISABLED
RUNLIST_ENABLED
MAX_RUNLIST_BUFFERS
struct fifo_runlist_info_gk20a

Rename
fifo_runlist_info_gk20a -> nvgpu_runlist_info

JIRA NVGPU-2012

Change-Id: Ib7e3c9fbf77ac57f25e73be8ea64c45d4c3155ff
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109008
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2019-05-02 23:39:42 -07:00
Thomas Fleury
258a6141fd gpu: nvgpu: rename runlist functions
Renamed:
- gk20a_runlist_reload -> nvgpu_runlist_reload
- gk20a_fifo_interleave_level_name -> nvgpu_runlist_interleave_level_name
- gk20a_runlist_update_for_channel -> nvgpu_runlist_update_for_channel
- nvgpu_fifo_lock_active_runlists -> nvgpu_runlist_lock_active_runlists
- nvgpu_fifo_unlock_active_runlists -> nvgpu_runlist_unlock_active_runlists
- nvgpu_fifo_get_runlists_mask -> nvgpu_runlist_get_runlists_mask
- nvgpu_fifo_unlock_runlists -> nvgpu_runlist_unlock_runlists
- gk20a_runlist_update -> nvgpu_runlist_update

Jira NVGPU-3198

Change-Id: Ifc5ad2aae546614667c174643ee07283d2716adc
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108029
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2019-04-30 12:46:02 -07:00
Seema Khowala
60633ca551 gpu: nvgpu: move gv11b rc code to rc_gv11b.c
Move chip specific recovery code for volta onwards
architecture to hal/rc/rc_gv11b.c

Rename
fifo.teardown_ch_tsg -> fifo.recover
gk20a_runlist_update_locked -> nvgpu_runlist_update_locked

Remove
Unused h/w headers from fifo_gv11b.c

Use local variable f instead of g->fifo

JIRA NVGPU-1314

Change-Id: Ia535bbe4780e7241fdd911a8f577c6b98cf0fe53
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2102897
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2019-04-24 20:23:06 -07:00
Nicolas Benech
0435ca4eb3 gpu: nvgpu: fix MISRA 17.7 in nvgpu.common.hal.fifo.*
MISRA Rule-17.7 requires the return value of all functions to be
used. Fix is either to use the return value or change the function
to return void. This patch contains fixes for all 17.7 violations
in the following units:
- nvgpu.common.hal.fifo.runlist
- nvgpu.common.hal.fifo.fifo

JIRA NVGPU-3039

Change-Id: I9483f5cb623cfe36d6b26e41c33f124c24710c08
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2098765
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2019-04-19 19:04:05 -07:00
Seema Khowala
da9dee85e2 gpu: nvgpu: move mmu fault handling to hal/fifo
Move chip specific mmu fault handling from
fifo_gk20a.c to hal/fifo/mmu_fault_gk20a.c

Move gk20a_teardown_ch_tsg to hal/rc/rc_gk20a.c

JIRA NVGPU-1314

Change-Id: Idf88b1c312bc9f46c2508f2c63e948d71d622297
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2094051
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2019-04-18 15:56:08 -07:00