Add unit tests for:
- gv11b_tsg_init_eng_method_buffers
- gv11b_tsg_deinit_eng_method_buffers
- gv11b_tsg_bind_channel_eng_method_buffers
- gv11b_tsg_unbind_channel_check_eng_faulted
Note: gv11b_tsg_enable was already tested as part of TSG common.
Added SWUTS documentation for above tests.
Modified gv11b_tsg_init_eng_method_buffers to inline computation
of method buffer size, as existing static function could never
return 0, making one branch not testable.
Added dummy IO register spaces for PFB, CE, PBUS and HSUB_COMMON,
so that g->ops.mm.init_mm_support can be called as part of
test_fifo_init_support. MM support is needed to test allocation
and mapping of DMA buffers.
Jira NVGPU-3788
Change-Id: I5356531b23c0456662187d16b35955bf0e528782
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2207384
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
channel and tsg units used to build object files from
upper fifo directory. But this was causing build
dependencies issues and stale .o files could be used.
Fixed this by building a shared library for nvgpu-fifo
for tmake makefiles.
Jira NVGPU-3480
Change-Id: I52c9e32b110c560fd445b8c854801f270364953d
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2151815
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ajesh K V <akv@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
channel and tsg units used to build object files from
upper fifo directory. But this was causing build
dependencies issues and stale .o files could be used.
Fixed this by building a shared library for nvgpu-fifo
for host makefiles.
Jira NVGPU-3480
Change-Id: I32655c207f48baa5cde40846ae5a276c7c8fa6fd
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2150370
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
Tested-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Fix the following MISRA rule violations in bitops unit,
MISRA Rule 10.1
MISRA Rule 10.3
MISRA Rule 10.4
MISRA Rule 11.8
MISRA Rule 21.2
Introduce nvgpu specific functions for bitops and bitmap operations
with unsigned integer as parameter for offset. OS specific type
conversions and handling of these inerfaces are taken care in the
respective OS files.
Jira NVGPU-3545
Change-Id: Ib1ef76563db6ba1d879a0b4d365b2958ea03f85c
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129513
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Updated test to cover test where:
- update runlist fails during unbind
- tsg is aborted
- updated runlist fails during abort
Modified update runlist stub to return -EINVAL depending
on branch combinations.
Added custom pruning function to skip some impossible
combinations of non-final branches.
Jira NVGPU-3476
Change-Id: I23a64085239b4003b73873a984a301476d73d962
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2124513
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Added coverage for
- nvgpu_tsg_open
- nvgpu_tsg_release
In order to cover branch combinatorial, a bitmask is used.
For each branch, one bit indicates if the branch is taken or not.
A loop calls the tested function with all combinations.
We could afterwards prune some combinations for branches that
directly exit the function.
Set MM_UNIFIED_MEMORY feature to avoid allocating from vidmem.
Jira NVGPU-3476
Change-Id: If2e82eabfa492b4c9ec727e175f31b53fbb4f5f1
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123156
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Added pre-populated register spaces for gv11b:
- NV_PFIFO 0x00003FFF:0x00002000
- NV_PTOP 0x000227FF:0x00022400
Registers values were captured on DDPX with reg_dump,
after disabling railgating and ELPG.
This allows running nvgpu_fifo_init_support, using
gv11b HALs.
Added the following tests:
- test_fifo_init_support
- test_tsg_open
- test_tsg_release
- test_fifo_remove_support
Jira NVGPU-3476
Change-Id: Ia717d9a9d431248635d51d0c265c16c2b6806a95
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120564
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
