Peter Daifuku
8f42de2775
gpu: nvgpu: channel_setup_bind: must be bound to TSG
...
In nvgpu_channel_setup_bind, return an error if the
channel isn't bound to a TSG, as future operations
rely on being bound.
Update usermode setup_bind test to bind channel to
the tsg before calling nvgpu_setup_bind
Manual port from rel-32
Bug 200543218
Change-Id: If33b01b8176c7488445c23080ad9d11f341bff43
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2215160
(cherry picked from commit 56f8e5b878https://git-master.nvidia.com/r/2218885
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com >
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com >
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com >
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2020-12-15 14:10:29 -06:00
Thomas Fleury
99ffa2622c
gpu: nvgpu: unit: add tests for TSG hal
...
Add unit tests for:
- gv11b_tsg_init_eng_method_buffers
- gv11b_tsg_deinit_eng_method_buffers
- gv11b_tsg_bind_channel_eng_method_buffers
- gv11b_tsg_unbind_channel_check_eng_faulted
Note: gv11b_tsg_enable was already tested as part of TSG common.
Added SWUTS documentation for above tests.
Modified gv11b_tsg_init_eng_method_buffers to inline computation
of method buffer size, as existing static function could never
return 0, making one branch not testable.
Added dummy IO register spaces for PFB, CE, PBUS and HSUB_COMMON,
so that g->ops.mm.init_mm_support can be called as part of
test_fifo_init_support. MM support is needed to test allocation
and mapping of DMA buffers.
Jira NVGPU-3788
Change-Id: I5356531b23c0456662187d16b35955bf0e528782
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2207384
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com >
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com >
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com >
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2020-12-15 14:05:52 -06:00
Thomas Fleury
c00d9f5c8a
gpu: nvgpu: unit: add SWUTS docs for nvgpu-runlist
...
This adds the SWUTS documentation for nvgpu-runlist unit tests:
- test_tsg_format_gen
- test_flat
- test_flat_oversize_tiny
- test_flat_oversize_single
- test_flat_oversize_onehalf
- test_flat_oversize_two
- test_flat_oversize_end
- test_interleaving_gen_all_run
- test_interleaving_l0
- test_interleaving_l1
- test_interleaving_l2
- test_interleaving_l0_l1
- test_interleaving_l1_l2
- test_interleaving_l0_l2
Jira NVGPU-3943
Change-Id: I569a936346a4726f506d338b54157212529c3be8
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2202477
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2020-12-15 14:05:52 -06:00
Debarshi Dutta
92a7ea7b01
gpu: nvgpu: remove non-safe code from unit tests
...
Remove branch F_CHANNEL_SETUP_BIND_HAS_GPFIFO_MEM from the unit test
for nvgpu_channel_setup_bind as gpfifo_mem belongs to KMD and are not
part of safe builds.
Remove assignment of stub_userd_setup_sw as USERD is compiled out for
safe build.
Jira NVGPU-3172
Change-Id: I4ba72043cb97d8804887c2bed30af9d01dca563e
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2142941
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com >
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com >
Reviewed-by: Alex Waterman <alexw@nvidia.com >
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com >
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2020-12-15 14:05:52 -06:00
Thomas Fleury
f779eb8e9a
gpu: nvgpu: unit: use allocated IO reg spaces
...
Statically initialized nvgpu_posix_io_reg_space structures are
used in test_fifo_setup_gv11b_reg_space to initialize register spaces.
If fifo, TSG and channel unit tests run concurrently, the same
register space structure can be registered multiple times for
different GPU contexts. This results in list corruption or
use of freed memory.
Use allocated register spaces instead.
Jira NVGPU-3943
Change-Id: I74c080f336e32149d2a378e2b15d37a2bd60ff71
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2204062
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com >
GVS: Gerrit_Virtual_Submit
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com >
Reviewed-by: Deepak Nibade <dnibade@nvidia.com >
Reviewed-by: Bibek Basu <bbasu@nvidia.com >
2020-12-15 14:05:52 -06:00
Thomas Fleury
5a6730de39
gpu: nvgpu: unit: add SWUTS docs for nvgpu-channel
...
This adds the SWUTS documentation for nvgpu-channel unit tests:
- test_channel_setup_sw
- test_channel_open
- test_channel_close
- test_channel_setup_bind
- test_channel_alloc_inst
- test_channel_from_inst
- test_channel_enable_disable_tsg
Jira NVGPU-3943
Change-Id: Ibfa1dbf144d3cb2c5836a5b1d1242dd0c35ca2e5
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2198892
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2020-12-15 14:05:52 -06:00
Thomas Fleury
bc0ee192e8
gpu: nvgpu: unit: add SWUTS docs for nvgpu-tsg
...
This adds the SWUTS documentation for nvgpu-tsg unit tests:
- test_tsg_open
- test_tsg_bind_channel
- test_tsg_unbind_channel
- test_tsg_release
- test_tsg_unbind_channel_check_hw_state
- test_tsg_unbind_channel_check_ctx_reload
- test_tsg_enable
- test_tsg_check_and_get_from_id
- test_tsg_abort
- test_tsg_setup_sw
Jira NVGPU-3943
Change-Id: Ia5222700b0320e03432a6afbbaae26ad2b32d704
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2197385
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2020-12-15 14:05:52 -06:00
Thomas Fleury
b8df5bcccd
gpu: nvgpu: unit: add SWUTS docs for nvgpu-fifo
...
This adds the SWUTS documentation for the nvgpu-fifo unit tests:
- test_fifo_init_support
- test_fifo_remove_support
Also added missing register space in remove support.
JIRA NVGPU-3943
Change-Id: I1f3a61cd41af0e8b78b0636adfb3448645e0fc15
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2195374
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2020-12-15 14:05:52 -06:00
Nicolas Benech
3bc55a1bf2
gpu: nvgpu: hal: remove non-FUSA runlist HALs from FUSA build
...
A number of gk20a_runlist HALs are not used in FUSA builds and are
removed by this patch. It also removes dependencies on those HALs
in the runlist unit test.
JIRA NVGPU-3690
Change-Id: If00bdedd59cf12e91609dd075c9732c6e80a05ff
Signed-off-by: Nicolas Benech <nbenech@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2174743
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-08-21 16:26:59 -07:00
Debarshi Dutta
48c00bbea9
gpu: nvgpu: rename channel functions
...
This patch makes the following changes
1) rename public channel functions to use nvgpu_channel prefix
2) rename static channel functions to use channel prefix
Jira NVGPU-3248
Change-Id: Ib556a0d6ac24dc0882bfd3b8c68b9d2854834030
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2150729
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-08-01 04:37:31 -07:00
Debarshi Dutta
92d009e796
gpu: nvgpu: add safety build flag CONFIG_NVGPU_SW_SEMAPHORE
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Added the safety build flag CONFIG_NVGPU_SW_SEMAPHORE to compile out
sw semaphore implementation in NVGPU. sw semaphore is only used for
presilicon bringup of GPU and hence is not needed for safety build.
Jira NVGPU-3172
Change-Id: I6a46ef22f1e2059437f710198f4ea49a47656fef
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2164216
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com >
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com >
Reviewed-by: Sagar Kamble <skamble@nvidia.com >
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com >
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-07-31 23:26:19 -07:00
Thomas Fleury
35b84884da
gpu: nvgpu: make userd optional for safety build
...
Most of userd code is only needed for kernel mode submit.
Compile out userd code if kernel submit is disabled.
Jira NVGPU-3537
Change-Id: Id7e5950f658695a266102b760a55d2f85ad3776c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2156322
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-07-24 17:04:53 -07:00
Thomas Fleury
46067384ba
gpu: nvgpu: unit: libnvgpu-fifo for tmake makefiles
...
channel and tsg units used to build object files from
upper fifo directory. But this was causing build
dependencies issues and stale .o files could be used.
Fixed this by building a shared library for nvgpu-fifo
for tmake makefiles.
Jira NVGPU-3480
Change-Id: I52c9e32b110c560fd445b8c854801f270364953d
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2151815
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ajesh K V <akv@nvidia.com >
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com >
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-07-16 16:15:59 -07:00
Thomas Fleury
5d6536b48f
gpu: nvgpu: unit: libnvgpu-fifo for host makefiles
...
channel and tsg units used to build object files from
upper fifo directory. But this was causing build
dependencies issues and stale .o files could be used.
Fixed this by building a shared library for nvgpu-fifo
for host makefiles.
Jira NVGPU-3480
Change-Id: I32655c207f48baa5cde40846ae5a276c7c8fa6fd
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2150370
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com >
Tested-by: Vedashree Vidwans <vvidwans@nvidia.com >
Reviewed-by: Adeel Raza <araza@nvidia.com >
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-07-12 11:25:10 -07:00
ajesh
b095d73022
gpu: nvgpu: modify the ffs and fls interface
...
Modify the ffs/fls interface function names to nvgpu_ffs and
nvgpu_fls. The return bit values are numbered from 1 to 64.
A return value of 0 indicates an input of 0 value.
Jira NVGPU-3601
Change-Id: I1c151eeac1f94fe3b5b85bd5daf0488f75c5efa0
Signed-off-by: ajesh <akv@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2146119
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com >
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com >
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com >
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com >
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-07-11 05:43:55 -07:00
Thomas Fleury
e8acd5fdfe
Revert "gpu: nvgpu: unit: stage some nvgpu_channel tests"
...
This reverts commit 6fb619aa30tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2138285
Reviewed-by: Alex Waterman <alexw@nvidia.com >
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nicolas Benech <nbenech@nvidia.com >
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com >
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-06-25 12:46:23 -07:00
Thomas Fleury
7092ff6055
gpu: nvgpu: unit: init setup_bind args
...
Make sure to initialize num_gpfifo_entries in setup_bind args.
Jira NVGPU-3651
Change-Id: Iad08c9838e4b85d066d83a16ea974b55e078547e
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2142503
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com >
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nicolas Benech <nbenech@nvidia.com >
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com >
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-06-25 12:46:14 -07:00
Thomas Fleury
06858c83d6
gpu: nvgpu: unit: stub userd.setup_sw
...
libnvgpu-drv can be compiled with NVGPU_USERD, while unit
test is not. Make sure we use the stub in any case.
Jira NVGPU-3480
Change-Id: Id48d1bda8796dd600f726233978e4f3c4b158674
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2140790
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com >
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com >
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com >
Reviewed-by: Alex Waterman <alexw@nvidia.com >
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-06-24 12:56:21 -07:00
Thomas Fleury
80a5b864d3
gpu: nvgpu: unit: zero-init vm for as bound channels
...
For some tests, we build ad-hoc structures to initialize ch->vm.
Make sure related vm and mm structures are zero-initialized to
avoid intermittent failures.
Jira NVGPU-3651
Change-Id: I20637e796a6f6b188f76c40aee918d2fa15490b1
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2140264
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com >
Reviewed-by: Sagar Kamble <skamble@nvidia.com >
Tested-by: Sagar Kamble <skamble@nvidia.com >
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com >
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-06-21 09:15:27 -07:00
Nicolas Benech
6fb619aa30
gpu: nvgpu: unit: stage some nvgpu_channel tests
...
The nvgpu_channel.setup_bind and enable_disable_tsg are causing
intermittent crashes in GVS, so stage them for now. Due to the
dependencies of the test functions, they just returns SUCCESS for now
(instead of disabling them entirely)
JIRA NVGPU-3640
Change-Id: I546b07b4633198f1a2c56e59e11eaa3355b1b285
Signed-off-by: Nicolas Benech <nbenech@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2136820
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com >
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com >
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com >
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-06-17 11:39:37 -07:00
Vedashree Vidwans
6f37ac5de2
gpu: nvgpu: Disable logging for safety build
...
This patch adds a conditional flag to filter out logging functions from
safety release build. Logging functions are replaced with stubs.
Jira NVGPU-869
Change-Id: If898b9ce8edb260727df28b407df83f0a92f61ad
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2109509
Reviewed-by: Alex Waterman <alexw@nvidia.com >
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com >
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-06-17 00:16:03 -07:00
Thomas Fleury
4d6aafe280
gpu: nvgpu: unit: stub l2_flush for channel setup bind
...
Stub g->ops.mm.l2_flush for channel setup bind, as calling HALs
is failing in GVS. This does not affect branch coverage for
this unit test.
Bug 2621189
Change-Id: I3a286f8d09456fe94c661d4be7140791a5ddca61
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2134652
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com >
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com >
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com >
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-06-12 09:45:41 -07:00
ajesh
a6cbfca58c
gpu: nvgpu: fix MISRA violations in bitops unit
...
Fix the following MISRA rule violations in bitops unit,
MISRA Rule 10.1
MISRA Rule 10.3
MISRA Rule 10.4
MISRA Rule 11.8
MISRA Rule 21.2
Introduce nvgpu specific functions for bitops and bitmap operations
with unsigned integer as parameter for offset. OS specific type
conversions and handling of these inerfaces are taken care in the
respective OS files.
Jira NVGPU-3545
Change-Id: Ib1ef76563db6ba1d879a0b4d365b2958ea03f85c
Signed-off-by: ajesh <akv@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2129513
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-06-11 22:26:41 -07:00
Sagar Kamble
3f08cf8a48
gpu: nvgpu: rename feature Make and C flags
...
Name the Make and C flag variables consistently wih syntax:
CONFIG_NVGPU_<feature name>
s/NVGPU_DEBUGGER/CONFIG_NVGPU_DEBUGGER
s/NVGPU_CYCLESTATS/CONFIG_NVGPU_CYCLESTATS
s/NVGPU_USERD/CONFIG_NVGPU_USERD
s/NVGPU_CHANNEL_WDT/CONFIG_NVGPU_CHANNEL_WDT
s/NVGPU_FEATURE_CE/CONFIG_NVGPU_CE
s/NVGPU_GRAPHICS/CONFIG_NVGPU_GRAPHICS
s/NVGPU_ENGINE/CONFIG_NVGPU_FIFO_ENGINE_ACTIVITY
s/NVGPU_FEATURE_CHANNEL_TSG_SCHED/CONFIG_NVGPU_CHANNEL_TSG_SCHED
s/NVGPU_FEATURE_CHANNEL_TSG_CONTROL/CONFIG_NVGPU_CHANNEL_TSG_CONTROL
s/NVGPU_FEATURE_ENGINE_QUEUE/CONFIG_NVGPU_ENGINE_QUEUE
s/GK20A_CTXSW_TRACE/CONFIG_NVGPU_FECS_TRACE
s/IGPU_VIRT_SUPPORT/CONFIG_NVGPU_IGPU_VIRT
s/CONFIG_TEGRA_NVLINK/CONFIG_NVGPU_NVLINK
s/NVGPU_DGPU_SUPPORT/CONFIG_NVGPU_DGPU
s/NVGPU_VPR/CONFIG_NVGPU_VPR
s/NVGPU_REPLAYABLE_FAULT/CONFIG_NVGPU_REPLAYABLE_FAULT
s/NVGPU_FEATURE_LS_PMU/CONFIG_NVGPU_LS_PMU
s/NVGPU_FEATURE_POWER_PG/CONFIG_NVGPU_POWER_PG
JIRA NVGPU-3624
Change-Id: I8b2492b085095fc6ee95926d8f8c3929702a1773
Signed-off-by: Sagar Kamble <skamble@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2130290
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-06-11 09:46:24 -07:00
Thomas Fleury
7bb278454f
gpu: nvgpu: unit: use 'ret' for return code
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Use 'ret' for return code, as 'rc' somehow maps to recovery
Jira NVGPU-3480
Change-Id: I31e0f3f30a9d6e4036a15e400acd71cb3a9bdfa7
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2132495
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com >
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com >
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com >
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-06-10 19:46:43 -07:00
Thomas Fleury
3136ad6a5b
gpu: nvgpu: unit: add channel enable/disable tsg test
...
Add unit test for the following functions:
- nvgpu_channel_enable_tsg
- nvgpu_channel_disable_tsg
Jira NVGPU-3480
Change-Id: I99dc24cb2089da8105cd66f3172984c49861a2e9
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2129728
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-06-10 19:46:24 -07:00
Thomas Fleury
9f9909fba8
gpu: nvgpu: unit: add channel ref from inst test
...
Add unit test for the following functions:
- nvgpu_channel_refch_from_inst_ptr
- nvgpu_channel_from_id
- nvgpu_channel_from_id__func
Jira NVGPU-3480
Change-Id: I04bffff7edc006ff5d822aa433684f93d5613a83
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2129727
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-06-10 19:46:09 -07:00
Thomas Fleury
99db6a6d3f
gpu: nvgpu: unit: add channel alloc/free inst tests
...
Add coverage for the following functions:
- nvgpu_channel_alloc_inst
- nvgpu_channel_free_inst
Jira NVGPU-3480
Change-Id: I754dccee69dfe04d5ae5607ad1deb6dd8c8de79f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2129726
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-06-10 19:45:54 -07:00
Thomas Fleury
5dbf0675f4
gpu: nvgpu: unit: add channel setup_bind tests
...
Add coverage for the following functions:
- nvgpu_channel_setup_bind
- nvgpu_channel_setup_usermode
Jira NVGPU-3480
Change-Id: I0814928851bb42a05402d3e99a66d30bd44cb0e6
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2129725
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-06-10 19:45:40 -07:00
Thomas Fleury
0624d908cd
gpu: nvgpu: unit: add channel close tests
...
Add branch coverage for:
- nvgpu_channel_kill
- nvgpu_channel_close
Also, modified gk20a_free_channel as follows:
- use nvgpu_assert to check ch->g (so that it can be tested)
- make sure g is non-NULL before calling nvgpu_get_poll_timeout
Jira NVGPU-3480
Change-Id: Ie1fa231b022da47b9ef9022ae67a6b3d73c28a8b
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2129724
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
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2019-06-10 19:45:17 -07:00
Thomas Fleury
1eef4eaae5
gpu: nvgpu: unit: add channel open tests
...
Add unit test for:
- gk20a_channel_open_new
Jira NVGPU-3480
Change-Id: I50d8cef746aa532712c94a3806822f5f0c7f435f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2129723
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com >
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-06-10 19:45:03 -07:00
Thomas Fleury
d2d7922411
gpu: nvgpu: unit: add channel setup_sw/cleanup_sw
...
Add unit test for:
- nvgpu_channel_setup_sw
- nvgpu_channel_cleanup_sw
Jira NVGPU-3480
Change-Id: Ic691b7fa17f97022fd7d4905377f9a348d8ecae8
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2129722
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-06-10 19:44:53 -07:00
Thomas Fleury
7e890f4285
gpu: nvgpu: unit: use 'ret' for return code
...
Use 'ret' for return code, as 'rc' somehow maps to recovery
Jira NVGPU-3476
Change-Id: Ife862ca5b049044adee69384ee805cd2271c0679
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2132490
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com >
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com >
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com >
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com >
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com >
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
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2019-06-09 22:56:42 -07:00
Thomas Fleury
f980c859e9
gpu: nvgpu: unit: cover more tsg open branches
...
Add branch coverage for:
- nvgpu_tsg_alloc_sm_error_states_mem
Jira NVGPU-3476
Change-Id: Ifca5b5f512536c609c11fc317d28704380a73a58
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2124514
Reviewed-by: Alex Waterman <alexw@nvidia.com >
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com >
Reviewed-by: Seema Khowala <seemaj@nvidia.com >
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com >
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2019-06-09 22:55:27 -07:00
Thomas Fleury
6602baaf41
gpu: nvgpu: unit: add tsg setup_sw/cleanup_sw coverage
...
Add unit test for:
- nvgpu_setup_sw
- nvgpu_cleanup_sw
Made nvgpu_tsg_init_support return void, since it cannot fail.
Jira NVGPU-3476
Change-Id: Ifff115e98c097375d7920b79ae9e13657d54a357
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2124512
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com >
Reviewed-by: Alex Waterman <alexw@nvidia.com >
Reviewed-by: Seema Khowala <seemaj@nvidia.com >
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com >
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-06-09 22:55:18 -07:00
Thomas Fleury
7eb8ea9764
gpu: nvgpu: unit: add tsg abort coverage
...
Add unit test for:
- nvgpu_tsg_abort
Jira NVGPU-3476
Change-Id: Ie1d93647e8ab239ad0604b04a3d36464b2bedb5b
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2124515
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com >
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2019-06-07 03:27:32 -07:00
Thomas Fleury
2b3f005313
gpu: nvgpu: unit: add tsg unbind branch coverage
...
Updated test to cover test where:
- update runlist fails during unbind
- tsg is aborted
- updated runlist fails during abort
Modified update runlist stub to return -EINVAL depending
on branch combinations.
Added custom pruning function to skip some impossible
combinations of non-final branches.
Jira NVGPU-3476
Change-Id: I23a64085239b4003b73873a984a301476d73d962
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2124513
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com >
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2019-06-07 03:27:23 -07:00
Thomas Fleury
32aa15f9d4
gpu: nvgpu: unit: add tsg enable/disable coverage
...
Add unit tests for
- g->ops.tsg.enable (gv11b_tsg_enable)
- g->ops.tsg_disable (nvgpu_tsg_disable)
Use an array to allow multiple stubs to store data.
Jira NVGPU-3476
Change-Id: I2afaef6d1ec4d74a05ec6e7952e5ead86c432f3d
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2123886
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com >
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-06-07 03:27:13 -07:00
Thomas Fleury
04cf2f1ba6
gpu: nvgpu: unit: add unit_assert helper
...
Add unit_assert helper to check condition.
In case of failure, the macro reports failed condition as well as
line number, then runs bail out code.
Jira NVGPU-3476
Change-Id: I9971e7fa0337661d46a06dfa05b67a98e3c46eee
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2129675
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com >
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
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2019-06-07 03:27:04 -07:00
Thomas Fleury
eb380fcbdb
gpu: nvgpu: unit: tmake userspace build for tsg
...
Added tmake userspace build for tsg
Added missing exports for libnvgpu-drv
Added tsg tests to required tests
Re-use fifo init/remove support
Jira NVGPU-3476
Change-Id: I5bcbbf5a9b58e825e1cad6aa5896de7e91fe7400
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2128160
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com >
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2019-06-07 03:26:54 -07:00
Thomas Fleury
741723e81a
gpu: nvgpu: unit: add test module for channel
...
Add unit test module for channel.
Move re-usable code at units/fifo level.
This included init and remove fifo support.
Added missing exports for libnvgpu-drv
Jira NVGPU-3480
Change-Id: Ibe4b423c3fb032b4add242d6c6dd705e43617b6e
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2126662
Reviewed-by: Nicolas Benech <nbenech@nvidia.com >
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com >
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2019-05-31 18:15:43 -07:00
Thomas Fleury
c6d51b20d5
gpu: nvgpu: unit: add unbind channel check_ctx_reload
...
Add test for nvgpu_tsg_unbind_channel_check_ctx_reload.
Check that force reload is done for other channel in TSG.
Jira NVGPU-3476
Change-Id: I1889442f81f2373127cc6db173a64eff6a07a981
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2123884
GVS: Gerrit_Virtual_Submit
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com >
Reviewed-by: Alex Waterman <alexw@nvidia.com >
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2019-05-31 11:16:22 -07:00
Thomas Fleury
53b82d5a84
gpu: nvgpu: unit: add unbind channel check_hw_state
...
Add coverage for nvgpu_tsg_unbind_channel_check_hw_state.
Jira NVGPU-3476
Change-Id: Ie1fcea234bb234a757ce4cc3b21d51b7b13c4d03
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2123883
GVS: Gerrit_Virtual_Submit
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com >
Reviewed-by: Alex Waterman <alexw@nvidia.com >
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2019-05-31 11:16:12 -07:00
Thomas Fleury
4fad611cb9
gpu: nvgpu: unit: add tsg bind/unbind coverage
...
Add coverage for
- nvgpu_tsg_bind_channel
- nvgpu_tsg_unbind_channel
Added pruning mechanism to skip subtests that attempt to test
some branches after a final branch.
Jira NVGPU-3476
Change-Id: I8e9a865055f36bc237a510ff93ab5385d430f5d1
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2121251
GVS: Gerrit_Virtual_Submit
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com >
Reviewed-by: Alex Waterman <alexw@nvidia.com >
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2019-05-31 11:16:03 -07:00
Thomas Fleury
29fc98550b
gpu: nvgpu: unit: add tsg open/release coverage
...
Added coverage for
- nvgpu_tsg_open
- nvgpu_tsg_release
In order to cover branch combinatorial, a bitmask is used.
For each branch, one bit indicates if the branch is taken or not.
A loop calls the tested function with all combinations.
We could afterwards prune some combinations for branches that
directly exit the function.
Set MM_UNIFIED_MEMORY feature to avoid allocating from vidmem.
Jira NVGPU-3476
Change-Id: If2e82eabfa492b4c9ec727e175f31b53fbb4f5f1
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2123156
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com >
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-05-31 11:15:53 -07:00
Thomas Fleury
0a2bac5974
gpu: nvgpu: unit: add io callbacks for tegra fuses
...
Remove WAR to set FMODEL during gv11b_init_hal.
Instead, add io callbacks for tegra fuses, and return
GCPLEX_CONFIG_WPR_ENABLED_MASK for FUSE_GCPLEX_CONFIG_FUSE_0.
Jira NVGPU-3476
Change-Id: I0739d66668b0f5c6658346b67bc368682edda4da
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2120680
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com >
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com >
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com >
Reviewed-by: Alex Waterman <alexw@nvidia.com >
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-05-24 19:05:47 -07:00
Thomas Fleury
77a5d43365
gpu: nvgpu: unit: add USERMODE reg space
...
Added pre-populated register space for gv11b:
- NV_USERMODE 0x0081FFFF:0x00810000
Added clean up in case of failure when registering
gv11b register spaces.
Jira NVGPU-3476
Change-Id: Iee5790390a4b91f2f7440305d10177c890f12154
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2121252
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com >
Reviewed-by: Alex Waterman <alexw@nvidia.com >
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-05-24 19:05:38 -07:00
Thomas Fleury
7b3950f224
gpu: nvgpu: unit: add FUSE reg space
...
Added pre-populated register space for gv11b:
- NV_FUSE 0x00021fff:0x00021000
Registers values were captured for Xavier on DDPX platform,
using reg_dump, after disabling railgating and ELPG.
Jira NVGPU-3476
Change-Id: Ic96f06501c3e903aef7ed635a88005332758bbb6
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2120663
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com >
Reviewed-by: Alex Waterman <alexw@nvidia.com >
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-05-24 19:05:29 -07:00
Thomas Fleury
12db97bd5c
gpu: nvgpu: unit: add MASTER, CCSR and PBDMA reg spaces
...
Added pre-populated register spaces for gv11b:
- NV_PCCSR 0x0080FFFF:0x00800000
- NV_PMC 0x00000FFF:0x00000000
- NV_PPBDMA 0x0005FFFF:0x00040000
Registers values were captured for Xavier on DDPX platform,
using reg_dump, after disabling railgating and ELPG.
Also added missing reg space unregistration for NV_TOP.
Jira NVGPU-3476
Change-Id: I8745f820819c1201846472602d7ef1872583ef4e
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2120657
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com >
Reviewed-by: Alex Waterman <alexw@nvidia.com >
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-05-24 19:05:20 -07:00
Thomas Fleury
20d611b081
gpu: nvgpu: unit: move gv11b reg spaces to unit/fifo
...
Move gv11b reg spaces initializations to unit/fifo, so that
it can be re-used by all fifo sub-units.
Jira NVGPU-3476
Change-Id: I9dd8564e71cb1b4c90a6a7df856e6eeadfedc649
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2120585
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com >
Reviewed-by: Alex Waterman <alexw@nvidia.com >
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com >
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com >
2019-05-24 19:05:11 -07:00
