-Renamed ACR structs for FUSA, ACR FUSA code has struct names
ending with _v1 & ACR non-FUSA with _v0, removed _v1 for FUSA
code to keep struct without any versioning for doxygen.
-Renamed acr_blob_construct_v1.c/h to acr_blob_construct.c/h
JIRA NVGPU-2516
Change-Id: Id2d5e48e8169ce59371c2b08d04c5a65ba94c685
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2218265
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Add NVGPU_INIT_TABLE_ENTRY for nvgpu_sw_quiesce_init_support.
Add g->sw_quiesce_init_done to avoid multiple initializations,
and check if deinit is needed in nvgpu_sw_quiesce_remove_support.
This avoids issues in common.init unit tests.
Jira NVGPU-4089
Change-Id: Ife3aa43d5f1f86899a895e4576e38ecc28a8e371
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2217779
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For MMU and PBDMA faults, error notifier needs to be set
before entering SW quiesce. Otherwise it ends up with
default NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT.
Added nvgpu_rc_mmu_fault to:
- call g->ops.fifo.recover when recovery is enabled
- set MMU error when recovery is disabled
Updated nvgpu_rc_pbdma_fault to set PBDMA error when
recovery is disabled as well.
Wait for deferred interrupts to complete before actually
entering SW quiesce state, to make sure error notifier has
been set.
Jira NVGPU-4127
Change-Id: Ia84c723e021e397391c6c609d4bb96c06afdcc47
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2210909
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Disable CONFIG_NVGPU_RECOVERY for safety build.
Uncorrectable errors will cause the GPU to be put gracefully into
a non-functioning state to ensure that no corrupted work is
completed because of the fault. This is because the freedom
from interference may not always be shown between the faulted and
the non-faulted TSG contexts.
Jira NVGPU-4089
Change-Id: Ice60722a3be3df980ac81c26f1370f22192bab36
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2197255
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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nvgpu.common.unit was just an enum used for passing to nvgpu.common.mc
APIs. So, move the enum into mc.h, and replace the include of unit.h
with mc.h where appropriate. And update the yaml arch.
JIRA NVGPU-4144
Change-Id: I210ea4d3b49cd494e43add1b52f3fbcdb020a1e3
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
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pbdma gops being called outside of fifo unit are:
1) common/ce/ce_app.c : g->ops.pbdma.format_gpfifo_entry
ce_app is dGPU specific.
2) os/linux/debug.c : g->ops.pbdma.dump_status
debug dump is non_fusa.
3) os/linux/cde.c : g->ops.pbdma.format_gpfifo_entry
cde is linux specific and is compiled out with
CONFIG_NVGPU_SUPPORT_CDE.
JIRA NVGPU-4111
Change-Id: I5bdf30f9ff45a38ea683692be65455d5ca2e1d48
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2215939
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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Add doxygen support to following functions.
- gr_prepare_sw
- gr_enable_hw
- gr_init_support
- gr_suspend
In ecc subunit
- ecc_init_support
- ecc_remove_support
- detect
In setup subunit
- alloc_obj_ctx
- free_gr_ctx
- free_subctx
- set_preemption_mode
In falcon subunit
- read_fecs_ctxsw_mailbox
- dump_stats
- get_fecs_ctx_state_store_major_rev_id
- bind_instblk
- ctrl_ctxsw
In intr subunit
- nonstall_isr
- stall_isr
- flush_channel_tlb
In init subunit
- get_no_of_sm
- get_nonpes_aware_tpc
- wait_initialized
- fifo_access
- get_max_subctx_count
- detect_sm_arch
- get_supported__preemption_modes
- get_default_preemption_modes
Identified the hal ops not being called from outside
units. Placed those hals under @cond ... @endcond comments.
Each gr subunit structure definition is taken outside the
main gops_gr structure definition. This helps to give a
well structured doxygen document.
Removed unused gr.falcon hals for
submit_fecs_method_op
submit_fecs_sideband_method_op
Update doxygen comments for nvgpu_gr_enable_hw and
nvgpu_gr_intr_stall_isr functions.
Jira NVGPU-4107
Change-Id: I56a74ef07bcc21752a06e3a4f55442894bb9109f
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2214511
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tsg gops being called outside of fifo unit are:
1) g->ops.tsg.post_event_id
This is non_fusa.
2) g->ops.tsg.set_timeslice
This is non_fusa.
3) g->ops.tsg.enable
This is non_fusa.
4) g->ops.tsg.disable
This is non_fusa.
5) g->ops.tsg.force_reset
This is non_fusa.
JIRA NVGPU-4114
Change-Id: I4ba5c4a9dafb85ff6bc41e59d97d387128d1a007
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2215953
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Add documentation for ramin HALs that are called
from other units.
- set_gr_ptr
- set_big_page_size
- init_pdb
- init_subctx_pdb
- init_pdb_cache_war
- deinit_pdb_cache_war
- base_shift
- alloc_size
Jira NVGPU-4116
Change-Id: Idf678174b4d162dd70054e8ee2c3c427549f1cfd
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2213581
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When a method is submitted to the FECS ucode using
gm20b_gr_falcon_submit_fecs_method_op, the status of the operation
is updated in the mailbox register. The driver can choose to skip validation of
the return status by setting op.cond.ok/fail = GR_IS_UCODE_OP_SKIP. At present
the driver continues to check for mailbox status despite the flag being set and
eventually times out.
Update gm20b_gr_falcon_submit_fecs_method_op so that mailbox status check is
skipped if op.cond.ok/fail is set to GR_IS_UCODE_OP_SKIP.
Change-Id: I45514933898924debedd727dc0c83570755e5b12
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
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When virtualized, the guest OS has no direct access to
PMU functionality:
- Don't create debugfs entries that rely on PMU access
- Clean up PMU vgpu HAL entries that imply that PMU access
is supported
Bug 200543218
Change-Id: I12730b600802448a240f3de042760041d3ae7d29
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2213650
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Separate out common.therm as safe unit since it is being used for
gv11b.
Create new hal.therm_fusa as safe unit since it is needed for gv11b.
Create hal.therm as non-safe unit.
Change-Id: Ife1cd17364d703db5e6be662625286356a8d966e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2212927
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