Commit Graph

7378 Commits

Author SHA1 Message Date
Konsta Holtta
14577a339c gpu: nvgpu: cde: list for contexts, defer deletion
Instead of current preallocated array plus dynamically allocated
temporary contexts, use a linked list in LRU fashion, always storing
free contexts at the beginning of the list. Initialize the preallocated
contexts to the list and store dynamically allocated temporaries there
too for quick reuse as needed, with a delayed scheduled work for
deleting temporaries when the high load has diminished.

Bug 200040211

Change-Id: Ibc75a0150109ec9c44b2eeb74607450990584b18
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/562856
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:58 -07:00
Terje Bergstrom
b1088fe769 gpu: nvgpu: Use generic clk_get_rate
Instead of gk20a_clk_get_rate() use the generic clk_get_rate().

Bug 1567274

Change-Id: If955790408d2f4a5d917ea3993573ac3f254c7d3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/592094
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
2015-03-18 12:11:58 -07:00
Vijayakumar
3c6a6376de gpu: nvgpu: disable cg in mmu error handler
With CG enabled sometimes fifo could not be idled
during firmware load.

Bug 200042729

Change-Id: I43d7551c0c7c19314c52ac5f678afed8c6df6415
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/559077
Reviewed-by: Automatic_Commit_Validation_User
2015-03-18 12:11:58 -07:00
sujeet baranwal
5febd08ae7 gpu: kernel support for suspending/resuming SMs
Kernel support for allowing a GPU debugger to suspend and resume
SMs. Invocation of "suspend" on a given channel will suspend all
SMs if the channel is resident, else remove the channel form the
runlist. Similarly, "resume" will either resume all SMs if the
channel was resident, or re-enable the channel in the runlist.

Change-Id: I3b4ae21dc1b91c1059c828ec6db8125f8a0ce194
Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com>
Signed-off-by: Mayank Kaushik <mkaushik@nvidia.com>
Reviewed-on: http://git-master/r/552115
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:57 -07:00
Mayank Kaushik
3d313d0657 gpu: nvgpu: gm20b: halify tpc lookup
Since the number of TPCs is different between GM20B and GK20a,
the function to look up the number of TPCs needs to be halified.

Change-Id: I19dab9a7105814f86c08c92283a0bb70abb6aa00
Signed-off-by: Mayank Kaushik <mkaushik@nvidia.com>
Reviewed-on: http://git-master/r/500064
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:57 -07:00
Mayank Kaushik
50d76e9b91 gpu: nvgpu: gk20a: regops: resident channel check
Fix the code that checks if the channel passed in for
regops is resident by also accounting for the TSG id,
if the channel is part of a TSG.

Change-Id: I449344e2887a4de4d55122f4aae5d3d4efabf725
Signed-off-by: Mayank Kaushik <mkaushik@nvidia.com>
2015-03-18 12:11:57 -07:00
Mayank Kaushik
1ee103adf3 gpu: nvgpu: create a hal function for smpc war
Create a HAL function for applying the SMPC workaround.The workaround
is only needed on gk20a, and not on gm20b.

Change-Id: I9edc741df32ab7d1dad38ecc56f238828128bfef
Signed-off-by: Mayank Kaushik <mkaushik@nvidia.com>
Reviewed-on: http://git-master/r/539187
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:57 -07:00
Kenneth Adams
aec94d8093 gpu: nvgpu: T18x support
nvgpu framework and build for T18x

Bug 1567274

Change-Id: I77835302a1110573008869d1106eface512bb9b1
Signed-off-by: Ken Adams <kadams@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:57 -07:00
Terje Bergstrom
8371833f42 gpu: nvgpu: Per-chip interrupt processing
Move accesses to MC registers under HAL so that they can be
reimplemented per chip.

Do chip detection and HAL initialization only once.

Bug 1567274

Change-Id: I20bf2f439d267d284bfd536f1a1dfb5d5a2dce4c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/590385
2015-03-18 12:11:56 -07:00
Supriya
eb690cb391 gpu: nvgpu: Changes to support LS sig
Support added to send PMU and FECS signatures
to ACR ucode

Bug 200046413

Change-Id: Ie1babb640be20a697ad4d6dd18bd11161edb263c
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
2015-03-18 12:11:56 -07:00
Sam Payne
8c6a9fd115 Revert "gpu: nvgpu: GR and LTC HAL to use const structs"
This reverts commit 41b82e97164138f45fbdaef6ab6939d82ca9419e.

Change-Id: Iabd01fcb124e0d22cd9be62151a6552cbb27fc94
Signed-off-by: Sam Payne <spayne@nvidia.com>
Reviewed-on: http://git-master/r/592221
Tested-by: Hoang Pham <hopham@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mitch Luban <mluban@nvidia.com>
2015-03-18 12:11:56 -07:00
Terje Bergstrom
4f6dddcf78 gpu: nvgpu: Allow compression on 64k pages
Allow compression always when page size matches the big page
size for the context.

Bug 1558739

Change-Id: I27b0aed06c24d69bd1555626b9affb1149536615
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/590422
2015-03-18 12:11:55 -07:00
Sami Kiminki
abfc843557 gpu: nvgpu: Fix AS IOCTL return code for failed user write
Fix return code in gk20a_as_dev_ioctl() in case of failed
copy_to_user().

Change-Id: I8b86c0dfca92c8c508006dc33673ccd926497819
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/590813
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:55 -07:00
Konsta Holtta
8c5b39353e gpu: nvgpu: cde: move GK20A_CDE to platform data
CONFIG_GK20A_CDE has not even been used for enabling CDE, just for
initializing it at boot time, and it was disabled; initialization has
been done late when the engine is first used. Remove the config
setting and add information about CDE support in gk20a platform data,
forcing the initialization at boot time. Boot time init removes rare
race conditions when CDE would be initialized by first user.

Bug 200046882

Change-Id: I85d5fb73dc27acbbe203138d25f6e342de030d93
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/562855
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:55 -07:00
Terje Bergstrom
2d5ff668cb gpu: nvgpu: GR and LTC HAL to use const structs
Convert GR and LTC HALs to use const structs, and initialize them
with macros.

Bug 1567274

Change-Id: Ia3f24a5eccb27578d9cba69755f636818d11275c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/590371
2015-03-18 12:11:54 -07:00
Allen Yu
23a182aaa6 Revert "gpu: nvgpu: Do not wait for FE GO_IDLE"
This reverts commit ba69a53f2f9ec055d7e61a40352bb9e73ba136be
as it's causing regression in boot stress.

Bug 200049711

Change-Id: Iacdba4d1b3739fd60c5a289d30f076f60389e453
Signed-off-by: Allen Yu <alleny@nvidia.com>
Reviewed-on: http://git-master/r/590634
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:54 -07:00
Vijayakumar
748475df20 gpu: nvgpu: gm20b: Support secure FECS recovery
When falcons are secured use PMU commands to reload
FECS firmware.

Bug 200042729

Change-Id: I09f2472b16dac6a510dba067bce3950075973d5f
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/552544
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:52 -07:00
Terje Bergstrom
4739499f07 gpu: nvgpu: Sync gk20a and gm20b headers
Synchronize gk20a and gm20b headers. All registers which were added
to gk20a are now added to gm20b, and some registers that are unused
are removed.

Bug 1567274

Change-Id: Ia3b7958c148e495cbff420ee56bb448db0f58680
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/590313
GVS: Gerrit_Virtual_Submit
2015-03-18 12:11:52 -07:00
Terje Bergstrom
b5bb4f53db gpu: nvgpu: Enable clocks only if defined
Enable clocks only if they are defined. This prevents panic in cases
where clock does not need to be enabled explicitly.

Bug 1567274

Change-Id: I7113c6d874b61acc2646effda9c02d3d1817c531
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:51 -07:00
Sami Kiminki
be48f4a451 gpu: nvgpu: Sanitize gk20a_gr_handle_notify_pending
Sanitize cyclestats portion of gk20a_gr_handle_notify_pending() a bit
and fix infinite loop and buffer overrun bugs in case of malformed
cyclestate element headers. Also, convert WARN_ON:s to gk20a_err:s for
malformed headers since they are userspace problems and not worth
kernel stack traces.

Bug 1566834

Change-Id: I69fbd85efdb042c5f0e745fac55eeff3aee0faa8
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
2015-03-18 12:11:51 -07:00
Terje Bergstrom
13ca1676ef gpu: nvgpu: Split L2 size calculation per chip
gk20a and gm20b calculate L2 size with different parameters. Split
the function for calculating size so that it does not query GPU id.

Bug 1567274

Change-Id: I09510c1bf0286c9df125d74e51df322c32bde646
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:51 -07:00
Konsta Holtta
83f3c09510 gpu: nvgpu: create cde context dynamically as needed
When the preallocated buffer of cde contexts is full, allocate a new
temporary one dynamically. This needs to create a totally new command
buffer but fixes possible but rare lockups in case of circular
dependencies. The temporary is deleted after the channel job has
finished.

Bug 200040211

Change-Id: Ic18d1441e8574a3e562a22f9b9dfec1acdf72b71
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/552036
GVS: Gerrit_Virtual_Submit
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
2015-03-18 12:11:51 -07:00
Konsta Holtta
b564dc87b6 gpu: nvgpu: add update callback to gk20a channel
Add support for a callback function with user data pointer to be
scheduled from the end of gk20a_channel_update. The function and its
private data are supplied when opening a new channel.

Change-Id: Ib6b408855ea60d46a6a114a69c01904703019572
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/552014
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Tested-by: Arto Merilainen <amerilainen@nvidia.com>
2015-03-18 12:11:51 -07:00
Konsta Holtta
5ce4438380 gpu: nvgpu: find unused cde context instead of lru
When preparing a new job, loop initially through the small number of
preallocated contexts and try to find one that is already finished,
instead of blindly getting the next slot in lru order. If all have work
to do, select next in lru order. This reduces the possibility of a
deadlock between cde tasks.

Bug 200040211

Change-Id: Ib695c0a8e1bcec095d50ec4f2522f3aad39ce97b
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/552035
GVS: Gerrit_Virtual_Submit
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
2015-03-18 12:11:50 -07:00
Terje Bergstrom
492b60fa2e gpu: nvgpu: Set page size for generic gpu
Default page size was made configurable. Set the page
size for generic GPU, too.

Bug 1567274

Change-Id: I7aa2762e0f542ec7de68e588afb9c51a6443b44f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:50 -07:00
Terje Bergstrom
cc8e05c215 gpu: nvgpu: Fix build without Tegra clk framework
Do not build clock code if TEGRA_CLK_FRAMEWORK is not defined. Also
make GK20A_DEVFREQ depend on TEGRA_CLK_FRAMEWORK, and build scaling
governor only if GK20A_DEVFREQ is enabled.

Bug 1567274

Change-Id: I6ea1462e7a110fb46c9d66ceda71167cff19699e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/562475
2015-03-18 12:11:50 -07:00
Terje Bergstrom
fcf4a10799 gpu: nvgpu: VM size should be u64
VM size should not depend on CPU architecture. It should be always
u64.

Change-Id: I81539807f6674877fd04f0079b2bec05b2a0640d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/562466
2015-03-18 12:11:50 -07:00
Terje Bergstrom
4c12bbce39 gpu: nvgpu: Fix build break with no PM runtime
Bug 1567274

Change-Id: I6ca10e329a46edf859f5b22f18d0da9bc8f41cd6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/562474
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
2015-03-18 12:11:50 -07:00
Terje Bergstrom
3446d89539 gpu: nvgpu: Add ioctl to create new TSG
Add ioctl to nvhost-ctrl to create a new TSG.

Bug 200042993

Change-Id: Icdd0edb1d9e374740ace6da9eb3a10c57c62617a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:50 -07:00
Konsta Holtta
3f3844a11c gpu: nvgpu: select ucode boot init by signature
Compute a signature checksum for ctxsw ucode boot section and determine
the format of boot initialization data by it. This unifies gk20a and
gk20b ucode segment loading a lot by separating the bootloader loading
logic to separate functions.

Note: Whenever the boot segment binary changes, its updated signature
must be added here. Management of different bootloaders must be
supported for repo-crossing staging issues.

Bug 1519397

Change-Id: I96f9b905d3631dfdebf71ea3a652a0968615fd0a
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/556679
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:49 -07:00
Konsta Holtta
a870ff1d29 gpu: nvgpu: Remove get and put client routines
gk20a_get_client() and gk20a_put_client() routines are effectively dead
code. The GPU has been using pm_runtime for reference counting whether
the device should be turned on or off, and gk20a_get_client() and
gk20a_put_client() have had no positive effect on the behaviour.

In worst case these functions trigger some issues as they may trigger
code paths that should not be run. There is also a race between get/put
and busy/idle.

This patch removes the functions and reworks as_gk20a.c to correctly use
gk20a_busy()/gk20a_idle() where put/get was required.

Additionally, finalize_poweron() is moved to gk20a_busy(), similarly as
it was with gk20a_get_client(). If pm_runtime is not in use, the device
is only powered on and never off. Currently this affects vgpu power
management since it does not use pm_runtime yet.

Bug 1562096

Change-Id: I3162655f83457e9caccd9264eed36b5d51e60c52
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/414998
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:49 -07:00
Konsta Holtta
23d15214ae gpu: nvgpu: allow building as a separate module
Include object files of gk20a, gm20b and vgpu in the same composite
object nvgpu.o in the top-level makefile, and remove the old makefiles.
This helps in building the driver as a separate module.

Bug 1476801

Change-Id: I93531c0f1a20e46904a429e492f8ed32e4f0c4a1
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/557971
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:49 -07:00
Terje Bergstrom
c1f8d68924 gpu: nvgpu: Do not wait for FE GO_IDLE
We do not need to wait for FE GO_IDLE counter to go to zero between
SW bundles.

Bug 1560770

Change-Id: I4cf53ea4e64b7244c589409d66c67ce8afb4a8d5
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/558305
2015-03-18 12:11:48 -07:00
Alex Frid
09cc99d33d gpu: nvgpu: Protect GM20b clock init from div-by-0
Protected GM20b clock initialization from div-by-0 in case when safe
fmax at Vmin is not known, and the respective interface returns zero.

Change-Id: I2064a3182c93f283c7e85c247601203dd1f71af4
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/559059
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2015-03-18 12:11:48 -07:00
Alex Frid
4a43c42229 dvfs: tegra21: Rename thermal safe maximum frequency
Renamed field and function operated on thermal safe maximum frequency
to make it clear that it is fmax at Vmin (not global fmax).

Change-Id: Ie2b5234e87dc5dc03ccdaeb2916f0b776e56b640
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/559058
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2015-03-18 12:11:47 -07:00
Terje Bergstrom
c2fbf8a54c gpu: nvgpu: Do not init interrupt mask
Interrupt mask init state is correct, so do not touch it.

Bug 1567274

Change-Id: I70673e406944823bd1cbfeee93ec75ce1e1af5da
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/558292
2015-03-18 12:11:47 -07:00
Terje Bergstrom
f2c905e482 gpu: nvgpu: vgpu: Fix vgpu mm code build break
Some fields were moved to vm specific fields from global mm fields.
Fix vgpu's mm code to follow that.

Zero page is never allocated in vgpu, so don't free it.

Change-Id: Ieabb33f1f004c9ffeeceabf61029b5bafc391889
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/559818
Reviewed-by: Automatic_Commit_Validation_User
2015-03-18 12:11:47 -07:00
Kirill Artamonov
1c47b239c1 gpu: nvgpu: remove register from whitelist
Userspace access to gr_pri_bes_crop_hww_esr removed
on Tegra platform.

Remove gr_pri_bes_crop_hww_esr register from gk20a whitelist.

bug 1456562

Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Change-Id: Id9c3f85e39c970182283a0cdbb87ac5b6b83a534
Reviewed-on: http://git-master/r/553636
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:47 -07:00
Konsta Holtta
1c8fb3178f gpu: nvgpu: cde: set err properly in oom condition
When gk20a_gmmu_map runs out of memory, set the error code before
returning early, so that caller knows about that cde load didn't succeed
and wouldn't use the bad context.

Change-Id: I1e166c78e39f07df941a29fc4e392a853d97a5c6
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/557273
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:47 -07:00
Terje Bergstrom
2eb6dcb469 gpu: nvgpu: Implement 64k large page support
Implement support for 64kB large page size. Add an API to create an
address space via IOCTL so that we can accept flags, and assign one
flag for enabling 64kB large page size.

Also adds APIs to set per-context large page size. This is possible
only on Maxwell, so return error if caller tries to set large page
size on Kepler.

Default large page size is still 128kB.

Change-Id: I20b51c8f6d4a984acae8411ace3de9000c78e82f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:46 -07:00
Terje Bergstrom
ecc6f27fd1 gpu: nvgpu: Common VM initializer
Merge initialization code from gk20a_init_system_vm(),
gk20a_init_bar1_vm() and gk20a_vm_alloc_share() into gk20a_init_vm().

Remove redundant page size data, and move the page size fields to be
VM specific.

Bug 1558739
Bug 1560370

Change-Id: I4557d9e04d65ccb48fe1f2b116dd1bfa74cae98e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:46 -07:00
Terje Bergstrom
5200902f57 gpu: nvgpu: Remove unused symbols
Remove unused symbols in platform file and gk20a.c.

Bug 1558739

Change-Id: If160a75061ecb4ad9cbc4abfb9bc409457299738
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:46 -07:00
Mahantesh Kumbar
1b6e655724 gk20a: Moved bind fecs to init_gr_support
-Moved bind fecs from work queue to init_gr_support.
-It makes all CPU->FECS communication to happen before
booting PMU, and after we boot PMU, only PMU talks to
FECS. So it removes possibility to race between CPU
and PMU talking to FECS.

Bug 200032923

Change-Id: I01d6d7f61f5e3c0e788d9d77fcabe5a91fe86c84
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/559733
2015-03-18 12:11:46 -07:00
Amit Sharma
7c35b023a7 gpu: nvgpu: gk20a: Fix non static symbol
Fixed sparse non static symbol warning by making the following symbol 'static':
- to_gk20a_sync_pt
- to_gk20a_timeline

Bug 200032218

Change-Id: Ie0310116aa1500ae8e4838b8a9ad4943a61cfc24
Signed-off-by: Amit Sharma <amisharma@nvidia.com>
Reviewed-on: http://git-master/r/552052
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2015-03-18 12:11:46 -07:00
Sami Kiminki
0858058e50 gpu: nvgpu: Report error on failed map
gk20a_vm_map_buffer() used to ignore silently map requests for
non-dmabuf fd:s. Fix this by returning the error code from
dma_buf_get().

Bug 1566862

Change-Id: If01b03f43b67b17d9fb997d914db871520f50c6e
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
2015-03-18 12:11:46 -07:00
Vijayakumar
c0b619c3cd gpu: nvgpu: gm20b: write gpccs start only once
Writing start bit twice can confuse falcon and
results in random behavior.

Bug 200040021

Change-Id: I62eb8e4632ac4fc471d931155471084ee0f9d0a4
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:45 -07:00
Seshendra Gadagottu
c414d4128d gpu: nvgpu: gm20b: fix issue with rail gating ref count
gpu rail gating reference count is going wrong because
"can_railgate" is set to false during probe(). For rail-gating
to work no gpu re-work is needed and by default rail-gating
is enabled with INT_MAX delay.

Bug 200044987

Change-Id: I9367275cd18c34cb19a51193353585789ba44c03
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/556568
Reviewed-by: Mitch Luban <mluban@nvidia.com>
2015-03-18 12:11:43 -07:00
Vijayakumar
17ce09bb05 gpu: nvgpu: send ELPG init cmd after GR is ready
bug 200040021
bug 200032923

Change-Id: I5aa7f4efb1b675e9a3faaf73a80452e55cded89e
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Change-Id: Ic162902bd2f05abab9ebd37392ed56dc4c164ba8
Reviewed-on: http://git-master/r/539995
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:43 -07:00
Konsta Holtta
026781c82c gpu: nvgpu: require mapped buffer be inside va
When validating buffers to be mapped, check that the buffer end does not
overflow over the virtual address node space.

Bug 1562361

Change-Id: I3c78ec7380584ae55f1e6bf576f524abee846ddd
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
2015-03-18 12:11:42 -07:00
Jussi Rasanen
835be94af5 gpu: nvgpu: cde: CDE optimizations
-Change cde_buf to use writecombined cpu mapping.
-Since reading writecombined cpu data is still slow, avoid reads in
  gk20a_replace_data by checking whether a patch overwrites a whole
  word.
-Remove unused distinction between src and dst buffers in cde_convert.
-Remove cde debug dump code as it causes a perf hit.

Bug 1546619

Change-Id: Ibd45d9c3a3dd3936184c2a2a0ba29e919569b328
Signed-off-by: Jussi Rasanen <jrasanen@nvidia.com>
Reviewed-on: http://git-master/r/553233
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Tested-by: Arto Merilainen <amerilainen@nvidia.com>
2015-03-18 12:11:42 -07:00