Commit Graph

108 Commits

Author SHA1 Message Date
Deepak Nibade
2489960344 gpu: nvgpu: remove redundant lock
"isr_enable_lock" was used to protect pmu's isr_enabled flag
and pmu enable/disable calls

Instead of this extra lock, we can reuse "isr_mutex" for this
purpose

Bug 200014542
Bug 200014887

Change-Id: Ifbb7d6108effc132266a20517820e470d52a7110
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/453348
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:10:47 -07:00
Supriya
cf69b50f96 nvgpu: gm20b: Changes for recovery path
Bug 200006956

Change-Id: I54b8ead007f8d671bcc731f73377986b880b9082
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: http://git-master/r/449343
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:10:42 -07:00
Supriya
e34b945834 nvgpu: new gpmu ucode compatibility
For LS PMU new ucode needs to be used.
Ucode has interface header file changes too.
This patch also has fixes for pmu dmem copy failure

Bug 1509680

Change-Id: I8c7018f889a82104dea590751e650e53e5524a54
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: http://git-master/r/441734
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:10:36 -07:00
Supriya
ebf7d4e25a nvgpu: Modify ACR host to use physical trancfg
PMU ucode and ACR ucode need 0th ctx dma to be programmed
for Physical access. To stay in sync with ucodes,
modified 0th transcfg to be physical access, and suitably
modified all other ctx dma's sent.

Bug 1509680
Change-Id: Ib3a24ebb8478488af57bb465d782e4045ca7d0d0
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: http://git-master/r/432084
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2015-03-18 12:10:19 -07:00
Terje Bergstrom
20408d5b32 gpu: nvgpu: Boot FECS to secure mode
Boot FECS to secure mode if ACR is enabled.

Bug 200006956

Change-Id: Ifc107704a6456af837b7f6c513c04d152b2f4d3a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/424251
2015-03-18 12:10:18 -07:00
Terje Bergstrom
7878824093 gpu: nvgpu: Separate PMU firmware load from init
Separate the code to load PMU firmware from the software init. This
allows folding ACR and non-ACR PMU software initialization sequences.

Bug 200006956

Change-Id: I74b289747852167e8ebf1be63036c790ae634da4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/424768
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
2015-03-18 12:10:17 -07:00
Terje Bergstrom
d46c8e4003 gpu: nvgpu: Remove extra g field in pmu_gk20a
pmu_gk20a has a pointer to struct gk20a *. As pmu_gk20a is part of
gk20a, there's no need to have the circular dependency.

Bug 200006956

Change-Id: I6d5d10a93b2fba4a26a1e28b3c5206506dc6cc04
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/424767
2015-03-18 12:10:17 -07:00
Supriya
b7793a493a nvgpu: Host side changes to support HS mode
GM20B changes in PMU boot sequence to support booting in
HS mode and LS mode

Bug 1509680

Change-Id: I2832eda0efe17dd5e3a8f11dd06e7d4da267be70
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: http://git-master/r/423140
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2015-03-18 12:10:14 -07:00