1. Register tegra-throttle cooling device as a
platform driver.
2. Obtain all the platform data (throtlle table
info) for all instances of blanced-throtlled cdev
from device tree and register them.
Change-Id: Ie92685eea3eb5cb18068b195adc9ab5f83762399
Signed-off-by: Arun Kumar Swain <arswain@nvidia.com>
Reviewed-on: http://git-master/r/449104
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Updated GM20B GPCPLL programming sequence to utilize new glitch-less
post divider:
- No longer bypass PLL for re-locking if it is already enabled, and
post divider as well as feedback divider are changing (input divider
change is still under bypass only).
- Use post divider instead of external linear divider to introduce
(VCO min/2) intermediated step when changing PLL frequency.
Bug 1450787
Signed-off-by: Alex Frid <afrid@nvidia.com>
Change-Id: I4fe60f8eb0d8e59002b641a6bfb29a53467dc8ce
Setup GPCPLL dynamic ramp coefficients based on update rate (instead
of hard-coding), since on GM20B high reference clock 38.4MHz allows
to use several update rates within supported range.
Bug 1450787
Change-Id: I0e14bcb8e3f65cc164fbb66b4adc688fcee9e2d6
Signed-off-by: Alex Frid <afrid@nvidia.com>
Moved GPCPLL locking under bypass procedure into separate function.
Added SYNC_MODE control during locking.
Bug 1450787
Change-Id: I8dbf9427fbdaf55ea20b6876750b518eb738de1b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Updated GPCPLL parameters according to GM20b specification.
Modified PLL programming, since on GM20b PLL post divider value is
equal to divider setting (which was not the case on GK20a this code
was inherited from).
Bug 1450787
Change-Id: Ia455ac49040047a3dbcd5d5211f2fbc71dc332ae
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/447751
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Tested-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
For LS PMU new ucode needs to be used.
Ucode has interface header file changes too.
This patch also has fixes for pmu dmem copy failure
Bug 1509680
Change-Id: I8c7018f889a82104dea590751e650e53e5524a54
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: http://git-master/r/441734
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Made GK20A and GM20B clock operations static, since they are invoked
only via HAL interfaces.
Bug 1450787
Change-Id: Ia30218ad4244bd8790b5ef96d1963678d0ba39e1
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/441710
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
gm20b_ltc_cbc_ctrl sent the wrong register value to
clear the CBC.
Bug 1507804
Change-Id: Ib0d867a122466e50cb15fef3b320fb2ee8455ef2
Signed-off-by: Wei Sun <wsun@nvidia.com>
Reviewed-on: http://git-master/r/435297
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Tested-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
PMU ucode and ACR ucode need 0th ctx dma to be programmed
for Physical access. To stay in sync with ucodes,
modified 0th transcfg to be physical access, and suitably
modified all other ctx dma's sent.
Bug 1509680
Change-Id: Ib3a24ebb8478488af57bb465d782e4045ca7d0d0
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: http://git-master/r/432084
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
We broadcast CBC operation to all LTCs, but we wait for only one
to finish.
Bug 1507804
Change-Id: Ib10aa5fe3a34b31862b2d5162c77441f7444a7ba
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/428123
Separate the code to load PMU firmware from the software init. This
allows folding ACR and non-ACR PMU software initialization sequences.
Bug 200006956
Change-Id: I74b289747852167e8ebf1be63036c790ae634da4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/424768
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Add a timeout mechanism to the L2 flushing code for gm20b.
Previously the code could spin forever in a loop if some
issue were to occur with the L2 causing the flush to fail.
Change-Id: I742c7671bac92aeb8e9674c43d30c45b2de4a836
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/423842
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
pmu_gk20a has a pointer to struct gk20a *. As pmu_gk20a is part of
gk20a, there's no need to have the circular dependency.
Bug 200006956
Change-Id: I6d5d10a93b2fba4a26a1e28b3c5206506dc6cc04
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/424767
Implement a full L2 flush (clean and invalidate) for gm20b in
the fifo recovery path.
Bug 1512176
Change-Id: Ibf89ede9cca65a6868ebff89825869053302a007
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/416435
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Add the necessary cache management registers for doing a
full L2 flush in GM20b.
Bug 1512176
Change-Id: I7799e5e584238a0af02abbf4f49917d7590d97dc
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/417260
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
When exiting rail gate, we reloaded default ZBC values. The correct
behavior is to reload the values.
Bug 1447255
Change-Id: I7aad3586dda91a91a3629062a27001af281b955e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/418346
For GM20B alone, the LTC count is already accounted for the HW logic
for the CBC base calculation from the postDivide address. So SW
doesn't have to explicity divide it by the LTC count in the postDivide
address calculation.
Bug 1477079
Change-Id: I558bbe66bbcfb7edfa21210d0dc22c6170149260
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/414264
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
ELPG flush is initiated from a common broadcast register, but must be
waited on via per-L2 registers. Split gk20a and gm20b versions of
the flush.
Change-Id: I75c2d65e8da311b50d35bee70308b60464ec2d4d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/401545
Reviewed-by: Automatic_Commit_Validation_User
Add support for booting FECS and GPCCS via faster bootloader method.
We leave this disabled until the bootloader binaries are checked in.
Change-Id: I39df5d116f7a33486407518c743638b01923970d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/413005
CBC frontdoor access works incorrectly in the simulator if CBC
is allocated from IOVA. This patch makes CBC allocation to happen
from physical memory if are running in simulator.
Bug 1409151
Change-Id: Ide08f4eab6911adc5737001c6d751ee227fec8f9
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/401544
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
update headers from latest gen_register/ip_check info
Change-Id: Iae892ab7138e7bba4abc821b9d7893e768647daa
Signed-off-by: Ken Adams <kadams@nvidia.com>
Reviewed-on: http://git-master/r/399382
the CBC clean and invalidate is done for gk20a for bug 1409151, now
it's time to do the same fo gm20b. the text of this change is
strictly copied from gk20a, simply to make build pass.
Change-Id: Id717cb1e2ca0fa3f8483c3fd40d7629a9cc85ec9
Signed-off-by: Bo Yan <byan@nvidia.com>
