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23 Commits

Author SHA1 Message Date
Lakshmanan M
2a6fcec078 gpu: nvgpu: add gr manager ops-2 and mig infra-2 
This CL covers the code changes related to following support,
 - Enabled gr manager ops.
 - Added gr manager init/remove support.
 - Refactor in gpu instance config infra.
 - Refactor in gr syspipe gpcs config infra.

JIRA NVGPU-5645
JIRA NVGPU-5646

Change-Id: Ib2fab2796d76fe105fc5a08f2c5f9bfa36317f7c
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2393550
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
vinodg
a126e00e28 gpu: nvgpu: compile out unused code in gr init unit 
Add CONFIG_NVGPU_GRAPHICS check before calling
g->gops>gr.init.preemption_state function.

Add NULL checking of pointer before deferecing those
pointers in de_init functions

Jira NVGPU-4676

Change-Id: Id9be0aebdcab4a8fb2b03e92e67c1c207b5b8eab
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: http://git-master.nvidia.com/r/c/linux-nvgpu/+/2276898
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Scott Long
7378e16778 gpu: nvgpu: gr: misra 12.1 fixes 
MISRA Advisory Rule states that the precedence of operators within
expressions should be made explicit.

This change removes the Advisory Rule 12.1 violations from gr code.

Jira NVGPU-3178

Change-Id: I99a60f60f6edcc2acb7343c66d1c4c79752d4acb
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: http://git-master.nvidia.com/r/c/linux-nvgpu/+/2276774
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Lakshmanan M
1c991a58af gpu: nvgpu: Add SM diversity support 
To achieve permanent fault coverage, the CTAs launched by
each kernel in the mission and redundant contexts must execute on
different hardware resources. This feature proposes modifications
in the software to modify the virtual SM id to TPC mapping across
the mission and redundant contexts. The virtual SM identifier to TPC
mapping is done by nvgpu when setting up the patch context.

The recommendation for the redundant setting is to offset the
assignment by one TPC, and not by one GPC. This will ensure that both
GPC and TPC diversity. The SM and Quadrant diversity will happen
naturally. For kernels with few CTAs, the diversity is guaranteed
to be 100%. In case of completely random CTA allocation,
e.g. large number of CTAs in the waiting queue, the diversity is
1 - 1/#SM, or 87.5% for GV11B, 97.9% for TU104.

Added NvGpu CFLAGS to enable/disable the SM diversity support
"CONFIG_NVGPU_SM_DIVERSITY".

This support is only enabled on gv11b and tu104 QNX non safety build.

JIRA NVGPU-4685

Change-Id: I8e3eaa72d8cf7aff97f61e4c2abd10b2afe0fe8b
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2268026
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Deepak Nibade
c7fa4109a8 gpu: nvgpu: remove extra semicolon in nvgpu_gr_config_init() 
Extra semicolon showed up as extra statement for which coverage was
missing as per Vectorcast. Remove the extra semicolon.

Jira NVGPU-4778

Change-Id: Id0135511a50d88c9a3ca5447dd6ebfd3dd9fa52d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2276344
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
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 2020-12-15 14:10:29 -06:00
vinodg
6b7c3c6d81 gpu: nvgpu: compile out unused gr.config code for safety build 
get_gpc_mask hal is set only for tu104. Add CONFIG_NVGPU_DGPU check
in the code for using that hal.

gr_config_alloc_struct_mem function is called from nvgpu_gr_config_init
gr_config_free_mem is called gr_config_alloc_struct_mem on failure.
No need to call gr_config_free_mem from nvgpu_gr_config_init again
for failure.

nvgpu_gr_config_init allocate nvgpu_gr_config struct.
config->sm_to_cluster will never get allocated before.So no need to
check for config->sm_to_cluster and do a memset.

Jira NVGPU-4531

Change-Id: I928041c110019bec885f9d5b6978db3032bc493c
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2262229
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Adeel Raza
252ddc4f05 gpu: nvgpu: add coverity whitelisting support 
Add macros for whitelisting coverity violations. These macros use pragma
directives. The pragma directives and whitelisting macros are only
enabled when a coverity scan is being run.

The whitelisting macros have been added to a new header called
static_analysis.h. The contents of safe_ops.h (CERT C safe ops) have
been moved into static_analysis.h because this will be the new header
for static analysis related macros/defines/etc.

JIRA NVGPU-3820

Change-Id: I9c63f20f670880b420415535738034619314b7c3
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2180600
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:05:52 -06:00
vinodg
d6a07e048e gpu: nvgpu: code update in gr_config for test 
Avoid code replication in nvgpu_gr_config_deinit function
Reuse gr_config_free_mem function in nvgpu_gr_config_deinit function.

Jira NVGPU-3582

Change-Id: I5325de5d30d2f9b05b499a1beb1e14110d905fd1
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2176378
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-08-16 17:55:51 -07:00
Scott Long
f6fc8a0540 gpu: nvgpu: gr: fix misra 2.7 violations 
Eliminate several Advisory Rule 2.7 violations in gr code.

Advisory Rule 2.7 states that there should be no unused
parameters in functions.

Jira NVGPU-3178

Change-Id: I415023a297031884b2d1be667551de2a7d8f23ad
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2174007
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2019-08-13 14:15:06 -07:00
Vinod G
149f9d826a gpu: nvgpu: fix cert int30 error in gr unit 
Fix CERT INT30-C violation in gr unit
Ensure the unsigned integer operations do not wrap.

Jira NVGPU-3854

Change-Id: I2d95eef97aeee0f9bd01f66f13cfc11d2834b550
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2169624
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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 2019-08-07 14:07:00 -07:00
Vinod G
cfd1aa3a76 gpu: nvgpu: reduce code complexity in gr_config file 
Reduce the code complexity of nvgpu_gr_config_init from
31 to 8.
Split the function to following sub functions with complexity
gr_config_init_pes_tpc(complexity : 3)
gr_config_init_gpc_skip_mask(complexity : 7)
gr_config_log_info(complexity : 9)
gr_config_set_gpc_mask(complexity : 2)
gr_config_alloc_valid(complexity : 6)
gr_config_free_mem(complexity : 2)
gr_config_alloc_struct_mem(complexity : 7)
nvgpu_gr_config_init(complexity : 8)

Jira NVGPU-3661

Change-Id: Ib67fca8f2b7d6e2817e3f4d2f89581a3ae21fbdb
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2145530
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2019-07-09 13:35:53 -07:00
Sagar Kamble
3f08cf8a48 gpu: nvgpu: rename feature Make and C flags 
Name the Make and C flag variables consistently wih syntax:
CONFIG_NVGPU_<feature name>

s/NVGPU_DEBUGGER/CONFIG_NVGPU_DEBUGGER
s/NVGPU_CYCLESTATS/CONFIG_NVGPU_CYCLESTATS
s/NVGPU_USERD/CONFIG_NVGPU_USERD
s/NVGPU_CHANNEL_WDT/CONFIG_NVGPU_CHANNEL_WDT
s/NVGPU_FEATURE_CE/CONFIG_NVGPU_CE
s/NVGPU_GRAPHICS/CONFIG_NVGPU_GRAPHICS
s/NVGPU_ENGINE/CONFIG_NVGPU_FIFO_ENGINE_ACTIVITY
s/NVGPU_FEATURE_CHANNEL_TSG_SCHED/CONFIG_NVGPU_CHANNEL_TSG_SCHED
s/NVGPU_FEATURE_CHANNEL_TSG_CONTROL/CONFIG_NVGPU_CHANNEL_TSG_CONTROL
s/NVGPU_FEATURE_ENGINE_QUEUE/CONFIG_NVGPU_ENGINE_QUEUE
s/GK20A_CTXSW_TRACE/CONFIG_NVGPU_FECS_TRACE
s/IGPU_VIRT_SUPPORT/CONFIG_NVGPU_IGPU_VIRT
s/CONFIG_TEGRA_NVLINK/CONFIG_NVGPU_NVLINK
s/NVGPU_DGPU_SUPPORT/CONFIG_NVGPU_DGPU
s/NVGPU_VPR/CONFIG_NVGPU_VPR
s/NVGPU_REPLAYABLE_FAULT/CONFIG_NVGPU_REPLAYABLE_FAULT
s/NVGPU_FEATURE_LS_PMU/CONFIG_NVGPU_LS_PMU
s/NVGPU_FEATURE_POWER_PG/CONFIG_NVGPU_POWER_PG

JIRA NVGPU-3624

Change-Id: I8b2492b085095fc6ee95926d8f8c3929702a1773
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130290
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-06-11 09:46:24 -07:00
Vinod G
0c13e9e8ad gpu: nvgpu: Fix CERT INT30-C errors in common.gr 
Fix CERT INT30-C erros in common.gr units

Unsigned integer operation may wrap. Use safe_ops macro
to fix the wrap errors.

Jira NVGPU-3585

Change-Id: I76127d8d58e1b5516370e78432754a7e7091e7be
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132588
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-10 07:48:58 -07:00
Vinod G
1ad54446da gpu: nvgpu: Add flag to map_tiles functions 
Add NVGPU_GRAPHICS flag to support the nvgpu_gr_config_init_map_tiles
and map_tiles related functions and variables.
Use only when this flag is defined.

Jira NVGPU-3583

Change-Id: Ib31a7445bcc573a127d1902bc19fc2aae9548d0f
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130616
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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 2019-06-05 22:56:12 -07:00
Vinod G
46a078f384 gpu: nvgpu: Add flag checking for ZCULL code in gr.config 
Add NVGPU_GRAPHICS flag checking for ZCULL specific codes in gr.config.
This flag is disabled for safety build now.

Jira NVGPU-3550

Change-Id: Ib15ccdcb083731207d0684e3de4b2f24e05edbcd
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128611
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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 2019-06-03 16:46:26 -07:00
Vinod G
61fb688f1a gpu: nvgpu: Add flag checking for ZCULL code 
Add NVGPU_GRAPHICS flag checking for ZCULL specific codes.
Define NVGPU_GRAPHICS flag for ZCULL support.
This flag is disabled for safety build now.

Jira NVGPU-3550

Change-Id: Ifd571a5e64e8fb2dfe02a87458a2986681900a6b
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127515
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 2019-05-31 04:08:11 -07:00
Vinod G
595da8ce67 gpu: nvgpu: Fix CERT-C errors in gr.config unit 
Fix CERT INT30-C errors in gr.config unit

cert_violation: Unsigned integer operation may wrap

Use safe_ops macro for multiplication to do wrap checks.

Jira NVGPU-3408

Change-Id: I553ca78263d687abf3d06b90588df9a83fd28815
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2126101
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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 2019-05-28 16:57:27 -07:00
Vinod G
cf2d37640d gpu: nvgpu: Fix CERT-C errors in gr.config unit 
Fix CERT INT30-C errors in gr.config unit

cert_violation: Unsigned integer operation may wrap

Use safe_ops macros for addition, multiplication and subtraction
to do wrap checks.

Jira NVGPU-3408

Change-Id: I96d9317eadcc747f493c27daec9ecab1f2fe36a2
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2125202
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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 2019-05-27 02:46:41 -07:00
Deepak Nibade
510b6cc8b2 gpu: nvgpu: fix MISRA 15.7 violation in gr.config unit 
Below MISRA 15.7 violation is reported in common.gr.config unit

nvgpu/drivers/gpu/nvgpu/common/gr/gr_config.c:169:
misra_violation: No non-empty terminating "else" statement.

Fix this by adding terminating "else" statement

Jira NVGPU-3225

Change-Id: Iaec3d6595da8fca55dfad8a8ccbcbad2ba7b1fe1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110987
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-06 13:15:30 -07:00
Deepak Nibade
3b0062bbd9 gpu: nvgpu: fix MISRA 5.7 violations in gr.config unit 
Below 5.7 violations are reported in common.gr.config unit :

nvgpu/drivers/gpu/nvgpu/common/gr/gr_config.c:628:
identifier_reuse: Identifier "sm_info" is already used to represent a type.

Fix them by renaming struct sm_info to struct nvgpu_sm_info

Jira NVGPU-3225

Change-Id: I26f70a4ed2a5a845e0dc9daeb8fb5474e35d42fb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110986
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-06 13:15:21 -07:00
Philip Elcan
596cf7241f gpu: nvgpu: gr: fix MISRA 10.4 violations 
MISRA Rule 10.4 requires both operands of an operator in which the
usual arithmetic conversions are performed shall have the same
essential type category.

JIRA NVGPU-3159

Change-Id: I7d864f407feadeb7ffed3922d68830aed777ce6f
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2104522
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: Adeel Raza <araza@nvidia.com>
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 2019-04-26 13:05:42 -07:00
Nitin Kumbhar
c649ca9fd6 gpu: nvgpu: move gr config structs to priv header 
Move sm_info and nvgpu_gr_config struts to a private
header and add APIs to access member fields.

JIRA NVGPU-3060

Change-Id: I90f44333f19cb8cb939c0a0f90d9a03f6c036080
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2091563
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 2019-04-10 15:04:21 -07:00
Nitin Kumbhar
55be80e697 gpu: nvgpu: clean gr config folder 
Move gr_config.c to gr directory and remove
gr/config directory as there are no additional
config files.

JIRA NVGPU-1884

Change-Id: I4238a3c25c16265036badf2c63b286e946deef4d
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2083699
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2019-03-28 07:04:52 -07:00