2 Commits

Author	SHA1	Message	Date
Tejal Kudav	b80b2bdab8	gpu: nvgpu: Add CE interrupt handling ... a. LAUNCH_ERR - Userspace error. - Triggered due to faulty launch. - Handle using recovery to reset CE engine and teardown the faulty channel. b. An INVALID_CONFIG - - Triggered when LCE is mapped to floorswept PCE. - On iGPU, we use the default PCE 2 LCE HW mapping. The default mapping can be read from NV_CE_PCE2LCE_CONFIG INIT value in CE refmanual. - NvGPU driver configures the mapping on dGPUs (currently only on Turing). - So, this interrupt can only be triggered if there is kernel or HW error - Recovery ( which is killing the context + engine reset) will not help resolve this error. - Trigger Quiesce as part of handling. c. A MTHD_BUFFER_FAULT - - NvGPU driver allocates fault buffers for all TSGs or contexts, maps them in BAR2 VA space and writes the VA into channel instance block. - Can be triggered only due to kernel bug - Recovery will not help, need quiesce d. FBUF_CRC_FAIL - Triggered when the CRC entry read from the method fault buffer does not match the computed CRC from the methods contained in the buffer. - This indicates memory corruption and is a fatal interrupt which at least requires the LCE to be reset before operations can start again, if not the entire GPU. - Better to quiesce on memory corruption CE Engine reset (via recovery) will not help. e. FBUF_MAGIC_CHK_FAIL - Triggered when the MAGIC_NUM entry read from the method fault buf does not match NV_CE_MTHD_BUFFER_GLOBAL_HDR_MAGIC_NUM_VAL - This indicates memory corruption and is a fatal interrupt - Better to quiesce on memory corruption f. STALLING_DEBUG - Only triggered with SW write for debug purposes - Debug interrupt, currently ignored Move launch error handling from GP10b to GV11b HAL as - 1. LAUNCHERR_REPORT errcode METHOD_BUFFER_ACCESS_FAULT is not defined on Pascal 2. We do not support GP10b on dev-main ToT JIRA NVGPU-8102 Change-Id: Idc84119bc23b5e85f3479fe62cc8720e98b627a5 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2678893 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>	2022-03-14 17:12:14 -07:00
Thomas Fleury	1160f083d4	gpu: nvgpu: move ce code to common/ce and hal/ce ... Merged gk20a_ce_delete_context and gk20a_ce_delete_context_priv. Renamed - gk20a_init_ce_support -> nvgpu_ce_init_support - gk20a_ce_destroy -> nvgpu_ce_destroy - gk20a_ce_suspend -> nvgpu_ce_suspend - gk20a_ce_create_context -> nvgpu_ce_create_context - gk20a_ce_delete_context -> nvgpu_ce_delete_context - gk20a_ce_execute_ops -> nvgpu_ce_execute_ops - gk20a_ce_prepare_submit -> nvgpu_ce_prepare_submit - gk20a_ce_put_fences -> nvgpu_ce_put_fences - gk20a_ce_delete_gpu_context -> nvgpu_ce_delete_gpu_context - gk20a_ce_get_method_size -> nvgpu_ce_get_method_size - gk20a_gpu_ctx -> nvgpu_ce_gpu_ctx - gk20a_gpu_ctx_from_list -> nvgpu_ce_gpu_ctx_from_list - gk20a_ce_app -> nvgpu_ce_app - gk20a_ce_debugfs_init -> nvgpu_ce_debugfs_init - gk20a_get_valid_launch_flags -> nvgpu_ce_get_valid_launch_flags - gk20a_ce2_isr -> gk20a_ce2_stall_isr - gp10b_ce_isr -> gp10b_ce_stall_isr - gv11b_ce_isr -> gv11b_ce_stall_isr Inlined - ce*_nonblockpipe_isr - ce*_blockpipe_isr - ce*_launcherr_isr Added ce_priv.h for ce private definitions. Moved files to common/ce and hal/fifo/ce - ce2.c -> common/ce2/ce.c - ce2_gk20a.c -> hal/ce/ce2_gk20a.c - ce2_gk20a.h -> hal/ce/ce2_gk20a.h - ce_gp10b.c -> hal/ce/ce_gp10b.c - ce_gp10b.h -> hal/ce/ce_gp10b.h - ce_gv11b.c -> hal/ce/ce_gv11b.c - ce_gv11b.h -> hal/ce/ce_gv11b.h Updated makefiles and #include directives Jira NVGPU-1992 Change-Id: Ia6064bf51b7a254085be43a112d056cb6fb6c3b2 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2093503 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-04-19 13:55:11 -07:00