Commit Graph

10 Commits

Author SHA1 Message Date
Richard Zhao
09cf3642ef gpu: nvgpu: add more compile flags to posix iGPU
Added bellow CFLAGS:
    -Werror -Wall -Wextra \
    -Wmissing-braces -Wpointer-arith -Wundef \
    -Wconversion -Wsign-conversion \
    -Wformat-security \
    -Wmissing-declarations -Wredundant-decls -Wimplicit-fallthrough

Also fixed all of compile errors for posix.

It's preparing for porting gpu server.

Jira GVSCI-11640

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: I30b09a62a57396abd642922e22f2e550a96f42c2
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2555059
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: Aparna Das <aparnad@nvidia.com>
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2022-01-13 12:36:31 -08:00
Vedashree Vidwans
78fb67bb0b gpu: nvgpu: move fuse definitions to fuse.h
Move common fuse definition macros to fuse.h. This will allow all
chip specific fuse files to use the common macros.

Jira NVGPU-6081

Change-Id: I85b5250809eef26a40f5b4b9bf6908dfa0d2be1f
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2422892
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2020-12-15 14:13:28 -06:00
Sagar Kamble
b117f40f6c gpu: nvgpu: separate tegra fuse read from under CONFIG_NVGPU_TEGRA_FUSE
tegra_fuse_readl is supported in upstream. Separate out the functions
using this API from the config CONFIG_NVGPU_TEGRA_FUSE.

Following four fuses are defined in downstream kernel repositories in
tegra fuse header. It can be incorporated in upstream if nvgpu starts
reading those fuses using nvmem APIs. Hence define those fuse offsets
in nvgpu itself for now.

1. FUSE_RESERVED_CALIB0_0
2. FUSE_GCPLEX_CONFIG_FUSE_0
3. FUSE_PDI0
4. FUSE_PDI1

Bug 200625647

Change-Id: I8da8c0c3a0682fdab806fa57035fedd29ef22c26
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2369955
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2020-12-15 14:13:28 -06:00
Sami Kiminki
d44960d424 gpu: nvgpu: add PDI reporting for GP10B (Linux)
Read the T186 SoC PDI fuse registers to retrieve the per-device
identifier for GP10B.

Bug 2957580

Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Change-Id: Ie5031a005ca251636614d27c2dc77bddfce0ea21
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2350930
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2020-12-15 14:13:28 -06:00
Alex Waterman
5f0fdf085c nvgpu: unit: Add new mock register framework
Many tests used various incarnations of the mock register framework.
This was based on a dump of gv11b registers. Tests that greatly
benefitted from having generally sane register values all rely
heavily on this framework.

However, every test essentially did their own thing. This was not
efficient and has caused a some issues in cleaning up the device and
host code.

Therefore introduce a much leaner and simplified register framework.
All unit tests now automatically get a good subset of the gv11b
registers auto-populated. As part of this also populate the HAL with
a nvgpu_detect_chip() call. Many tests can now _probably_ have all
their HAL init (except dummy HAL stuff) deleted. But this does
require a few fixups here and there to set HALs to NULL where tests
expect HALs to be NULL by default.

Where necessary HALs are cleared with a memset to prevent unwanted
code from executing.

Overall, this imposes a far smaller burden on tests to initialize
their environments.

Something to consider for the future, though, is how to handle
supporting multiple chips in the unit test world.

JIRA NVGPU-5422

Change-Id: Icf1a63f728e9c5671ee0fdb726c235ffbd2843e2
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335334
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2020-12-15 14:13:28 -06:00
Sagar Kamble
59c6947fc6 gpu: nvgpu: add CONFIG_NVGPU_TEGRA_FUSE
Encapsulate the tegra fuse functionality under the config flag
CONFIG_NVGPU_TEGRA_FUSE.

Bug 2834141

Change-Id: I54c9e82360e8a24008ea14eb55af80f81d325cdc
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306432
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2020-12-15 14:13:28 -06:00
Prateek sethi
5438e73cff gpu: nvgpu: SWUD for fuse unit
- Added SWUD for the FUSA code.
- Flagged out non safe code using CONFIG_NVGPU_NON_FUSA.

Jira NVGPU-3759

Change-Id: I43dd4438c017377995a2610578f2bbf554a147ac
Signed-off-by: Prateek sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2213965
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Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
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2020-12-15 14:10:29 -06:00
Thomas Fleury
0a2bac5974 gpu: nvgpu: unit: add io callbacks for tegra fuses
Remove WAR to set FMODEL during gv11b_init_hal.
Instead, add io callbacks for tegra fuses, and return
GCPLEX_CONFIG_WPR_ENABLED_MASK for FUSE_GCPLEX_CONFIG_FUSE_0.

Jira NVGPU-3476

Change-Id: I0739d66668b0f5c6658346b67bc368682edda4da
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120680
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-05-24 19:05:47 -07:00
Philip Elcan
cef9b8ff9d gpu: nvgpu: unit: fuse unit test for gp10b
This adds the initial unit test for the fuse module and testing for
gp10b. It verifies the exposed APIs for this device in the fuse module.

To allow the hal_init to pass before the HAL for
read_gcplex_config_fuse() can be overridden, the default behavior of the
POSIX implementation for nvgpu_tegra_fuse_read_gcplex_config_fuse() is
changed.

This provides 100% code and branch coverage for this unit/device.

JIRA NVGPU-938

Change-Id: I9efa8080c12ace637581c77aa35aab3f86a94760
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1943385
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2018-11-08 21:43:26 -08:00
Alex Waterman
b15624b39b gpu: nvgpu: posix: move the posix dir to os
Since the posix code is supporting a particular OS this code
should belong under os/ not common/.

Change-Id: Idf5f75b8ab9d614c9dd43ea23dab8df3c346c0ef
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1800658
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2018-08-17 13:54:25 -07:00