Commit Graph

11 Commits

Author SHA1 Message Date
Vinod G
4201f58e1e gpu: nvgpu: Add utils header for posix
Move all definitions and functions other than type defines from types.h
to new header utils.h for posix.
Update files that use functions and defintions from utils.h

DIV_ROUND_UP macro is updated to use safe_ops.h calls to handle
the CERT-C wrap issues.

Jira NVGPU-3411

Change-Id: I9da3e9f255f39949287c615519f062fd8816aa04
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130453
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
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2019-06-07 17:05:23 -07:00
Nitin Kumbhar
69331cdfb7 gpu: nvgpu: posix: fix EXP32 CERT C violation
Do not ignore volatile attribute of addr while assigning it to p.

Error: CERT EXP32-C:
drivers/gpu/nvgpu/os/posix/bitmap.c:227:
cert_violation: Access volatile variable "addr" through
 a nonvolatile reference.

Jira NVGPU-3560

Change-Id: I202b143e1818641b12f6552810953ac447348271
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2122720
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2019-06-06 16:27:13 -07:00
ajesh
8901faae57 gpu: nvgpu: fix MISRA violations in bitops unit
MISRA rule 21.1 states that #define and #undef shall not be used on
a reserved identifier or reserved macro name.  Fix violations of
rule 21.1 in bitops unit.
MISRA rule 21.2 states that a reserved identifier or macro name
shall not be declared.  Fix violations of rule 21.2 in bitops unit.

Jira NVGPU-3545

Change-Id: Ie551d7ce5e19287107403f2c991bcc55bd11a4e8
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2125842
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2019-05-29 14:51:37 -07:00
ajesh
ff4de9c9c1 gpu: nvgpu: fix issues with ffs and __fls
The LSB is position 1 for ffs and LSB is position 0 for __fls.  Fix the
issue with the return values of ffs and __fls to follow the mentioned
bit positions.

Jira NVGPU-2149

Change-Id: I4deab420c62217f8ad90683397c38530f88467d2
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107276
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
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2019-04-30 00:49:09 -07:00
Philip Elcan
13ad8142ef gpu: nvgpu: unit: fix valgrind errors in posix bitmap
Fix cases where valgrind reported conditional jump or move depends on
uninitialised value(s)

JIRA NVGPU-3098

Change-Id: I5699d1f8539ec29e6f1bac6452e216c72c4d9007
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2094640
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-04-12 15:34:10 -07:00
Philip Elcan
67caad40e9 gpu: nvgpu: unit: update misc atomics to use gcc builtins
There were a few outliers in the unit tests that were still using old
style atomics (__sync_*). This updates those to use the new standard
builtins in GCC.

JIRA NVGPU-2842

Change-Id: Ib79e0fb48e7812b57aa4634ad96c37436c2b3923
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2034217
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-03-07 19:04:29 -08:00
Adeel Raza
800d96865d gpu: nvgpu: posix: MISRA rule 15.6 fixes
MISRA rule 15.6 requires that all if/else/loop blocks should be enclosed
by brackets. This patch adds brackets to single line if/else/loop blocks
in the POSIX code.

JIRA NVGPU-775

Change-Id: Idafd5a5068c23b850ad1b0b083550a75b35588c1
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011739
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Scott Long <scottl@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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2019-02-05 19:23:58 -08:00
Amurthyreddy
9aa74d5f86 gpu: nvgpu: MISRA 10.4 boolean fixes
MISRA rule 10.4 doesn't allow arithmetic conversions on operands of
different essential type category.

Fix violations where an arithmetic conversion is performed on boolean
and non-boolean types.

JIRA NVGPU-994

Change-Id: I2af9937678462b632bb6ec6178e10d02104fc3bc
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1832337
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2018-10-30 15:33:58 -07:00
Adeel Raza
dc37ca4559 gpu: nvgpu: MISRA fixes for composite expressions
MISRA rules 10.6, 10.7, and 10.8 prevent mixing of types in composite
expressions. Resolve these violations by casting variables/constants to
the appropriate types.

Jira NVGPU-850
Jira NVGPU-853
Jira NVGPU-851

Change-Id: If6db312187211bc428cf465929082118565dacf4
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1931156
GVS: Gerrit_Virtual_Submit
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2018-10-25 11:13:38 -07:00
Philip Elcan
8c4b073537 gpu: nvgpu: posix: fix implementation of fls()
The POSIX implementation of fls() wasn't compliant with the Linux which
returns fls(0)=0 fls(1)=1, etc.

Bug found as result of JIRA NVGPU-1042.

Change-Id: Id0279e36332ffe236ed792c013c32f2da841f557
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1828361
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2018-09-20 12:58:50 -07:00
Alex Waterman
b15624b39b gpu: nvgpu: posix: move the posix dir to os
Since the posix code is supporting a particular OS this code
should belong under os/ not common/.

Change-Id: Idf5f75b8ab9d614c9dd43ea23dab8df3c346c0ef
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1800658
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2018-08-17 13:54:25 -07:00