Rename __nvgpu_set_enabled() to nvgpu_set_enabled(). The original
double underscore was present to indicate that this function is a
function with potentially unintended side effects (enabling a feature
has wide ranging impact).
To not lose this documentation a comment was added to convey that this
function must be used with care.
JIRA NVGPU-1029
Change-Id: I8bfc6fa4c17743f9f8056cb6a7a0f66229ca2583
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1989434
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With intention to make falcon header free of private data we are making
all falcon struct members (pmu.flcn, sec2.flcn, fecs_flcn, gpccs_flcn,
nvdec_flcn, minion_flcn, gsp_flcn) in the gk20a, pointers to struct
nvgpu_falcon. Falcon structures are allocated/deallocated by
falcon_sw_init & _free respectively.
While at it, remove duplicate gk20a.pmu_flcn and gk20a.sec2_flcn,
refactor flcn_id assignment and introduce falcon_hal_sw_free.
JIRA NVGPU-1594
Change-Id: I222086cf28215ea8ecf9a6166284d5cc506bb0c5
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1968242
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pmu.g & sec2.g were set in nvgpu_falcon_sw_init. They are now set
in nvgpu_early_init_pmu_sw & nvgpu_init_sec2_setup_sw. Pass gk20a
& pmu struct to nvgpu_init_pmu_fw_support like sec2.
pmu_fw_support & sec2_setup_sw are separated from respective init
sequence and now are called earlier since we need ->g member earlier
and most of the setup is sw only.
nvgpu_init_pmu_fw_ver_ops is now being exported.
JIRA NVGPU-1594
Change-Id: I6c71c6730ce06dad190159269e2cc60301f0237b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1968241
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The PMU pstate deinit was invoked part of gpu power off. This frees and clears
the pmgr_pmu struct which causes the pmu remove support to crash when it
tries to access the pmgr_pmu object for freeing up the pmu board objects.
Deferred pstate deinit to nvgpu driver removal as there is no reason for it be
invoked part of prepare poweroff sequence.
JIRA NVGPU-1618
Change-Id: I2eb52000f0732d0abed54946e0843367b119d443
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1971225
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MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.
Adding "U" at the end of the integer literals or casting operands
to have same type of operands when an arithmetic operation is
performed.
This fixes violations where an arithmetic operation is performed on
signed and unsigned int types.
JIRA NVGPU-992
Change-Id: I27e3e59c3559c377b4bd3cbcfced90fdf90350f2
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1921459
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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