This patch constructs an abstraction to hide the sync_fence
functionality from the common code. struct nvgpu_os_fence acts as an
abstraction for struct sync_fence.
struct nvgpu_os_fence consists of an ops structure named nvgpu_os_fence_ops
which contains an API to do pushbuffer programming to generate wait
commands for the fence.
The current implementation of nvgpu only allows for wait method on a
sync_fence which was generated using a similar backend(i.e. either
Nvhost Syncpoints or Semaphores). In this patch, a
generic API is introduced which will decide the type of the underlying
implementation of the struct nvgpu_os_fence at runtime and run the
corresponding wait implementation on it.
This patch changes the channel_sync_gk20a's semaphore specific
implementation to use the abstract API. A subsequent patch will make
the changes for the nvhost_syncpoint based implementations as well.
JIRA NVGPU-66
Change-Id: If6675bfde5885c3d15d2ca380bb6c7c0e240e734
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1667218
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We so far do not support unbinding a channel from TSG explicitly through IOCTL
Channel is unbound from TSG when channel fd is closed
But this could create issue in case process is forked and fd is duplicated
In worst case it is possible that duplicate fd is closed sometime later when
TSG is active and that could lead to corruption of TSG state
Fix this by implementing NVGPU_TSG_IOCTL_UNBIND_CHANNEL API
This API will simply call gk20a_tsg_unbind_channel() API to unbind the
channel
Note that we also mark the channel has_timedout since unbound channel does
not have any context of its own and it cannot serve any job
Remove call to gk20a_disable_channel() while closing the channel.
We do not support bare channels without TSG, and if channel is not part of TSG
then it means channel is already unbound from TSG with call to
NVGPU_TSG_IOCTL_UNBIND_CHANNEL, and there is nothing to do while closing the
channel
Bug 200327095
Jira NVGPU-229
Change-Id: Ib7f6710f0dc8125caafabe7bee737622c3dd9fa3
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1708902
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Split sim initialization to two parts,
first part gets invoked as part of probe and
second part gets invoked in the finalize_poweron
after the hal has been initialized.
This is done because some of the sim init
code uses mm api's which are assigned as
part of hal init.
replaced sim buffer allocation api's
with nvgpu_dma_sys_alloc.
Change-Id: Ib019fbb747bdf6dcc74e7deba732ab41f0869e96
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1705424
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Switch all logging to nvgpu_log*(). gk20a_dbg* macros are
intentionally left there because of use from other repositories.
Because the new functions do not work without a pointer to struct
gk20a, and piping it just for logging is excessive, some log messages
are deleted.
Change-Id: I00e22e75fe4596a330bb0282ab4774b3639ee31e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1704148
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segregated os-agnostic function from linux/sim.c and linux/sim_pci.c
to sim.c and sim_pci.c, while retaining os-specific functions.
renamed all gk20a_* api's to nvgpu_*.
renamed hw_sim_gk20a.h to nvgpu/hw_sim.h
moved hw_sim_pci.h to nvgpu/hw_sim_pci.h
JIRA VQRM-2368
Change-Id: I040a6b12b19111a0b99280245808ea2b0f344cdd
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
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PMU ucode is updated to include LDIV slowdown factor in gr_init_param command.
- Defined a new version gr_init_param_v2.
- Updated the PMU FW version code.
- Set the LDIV slowdown factor to 0x1e by default.
- Added sysfs entry to program ldiv_slowdown factor at runtime.
Bug 200391931
Change-Id: Ic66049588c3b20e934faff3f29283f66c30303e4
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1674208
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Add new HAL gops.mc.isr_nonstall() to handle nonstall interrupts
We already handle nonstall interrupts in nvgpu_intr_nonstall()
But this API is completely in linux specific code
Separate out os-independent code to handle nonstall interrupts in new API
mc_gk20a_isr_nonstall() and set it to HAL gops.mc.isr_nonstall() for all
existing chips
Call this HAL from nvgpu_intr_nonstall()
Jira NVGPUT-8
Change-Id: Iec6a56db03158a72a256f7eee8989a0a8a42ae2f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1706589
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Implement a worker thread to replace the workqueue based
handling for clk arbiter update callbacks.
The work items scheduled with the thread are of two types,
update_vf_table and arb_update. Previously, there were two
workqueues for handling these two work struct's separately.
Now the single worker thread would process these two events.
If a work item of a particular type is scheduled to be run
on the worker, another instance of same type won't be
scheduled, which mirrors the linux workqueue behavior.
This also removes dependency on linux workqueues/work struct
and makes code portable to be used by QNX also.
Jira VQRM-3741
Change-Id: Ic27ce718c62c7d7c3f8820fbd1db386a159e28f2
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
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RCU's are available only in (linux) kernel. Though they are
able to achieve lockless access in some specific scenarios,
they are heavily dependent on the kernel for their functionality.
E.g. synchronize_rcu(), which depends on the kernel in order to
delimit read side critical sections.
As such it is very difficult to implement constructs analogous
to RCUs in userspace code. As a result the code which depends on
RCU's for synchronization is not portable between OS'es,
especially if one of them is in userspace, viz. QNX.
Also, if the code is not in performance critical path, we can do
with non-RCU constructs.
For clk arbiter code here, RCU's are replaced by the traditional
spinlocks, so that the code could be used by QNX down the line.
Jira VQRM-3741
Change-Id: I178e5958788c8fd998303a6a94d8f2f328201508
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1705535
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In order to enable the movement of clk arbitrator to common
code, we need to remove the NVGPU_GPU_EVENT_* defines (which
are present in uapi) and instead use the common code defines.
Add a conversion function for the same.
With this the uapi header is no longer required to be included
inside clk_arb.c
Jira VQRM-3741
Change-Id: If01614b01733876046f98b97e70285c52bc33e45
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1699241
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- total DMA memory allocation is currently tracked by adding page aligned
size of nvgpu_mem
- The sequence is roughly as follows:
- total dma memory used += mem->aligned_size
- mem->aligned_size = PAGE_ALIGN(size)
- In above sequence, nvgpu_mem structure is initially zero when it is added
to total dma memory used after which it is assigned page aligned value
- This patch fixes total dma memory usage tracking.
Change-Id: Ibb879c8d38ae9077c3d198d9bb008a72e9208b4d
Signed-off-by: Deepak Bhosale <dbhosale@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1685312
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Clk arbiter code contains two significant portions -
the one which interacts with userspace and is OS specific,
and the other which does the heavylifting work which can
be moved to the common OS agnostic code.
Split the code into two files in prep towards refactoring
the clk arbiter.
Jira VQRM-3741
Change-Id: I47e2c5b18d86949d02d6963c69c2e2ad161626f7
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
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Cache the rate used in clk_set_rate().
Return that cached rate on clk_get_rate(), don't read from hardware.
This cached rate is used to avoid duplicate requests to clk_set_rate().
Motivation is to support multiple governors for gpu clk.
Reading clock from hardware is unreliable in multi-governor situation.
Relying on hardware clock value could mislead the kernel gpu governor
in its scaling calculations.
Bug 2051688
Change-Id: I43fc056eea6f69fe0889c45640fcb892b658071c
Signed-off-by: Arun Kannan <akannan@nvidia.com>
(cherry picked from commit 7f819a9ba7)
Reviewed-on: https://git-master.nvidia.com/r/1662759
Reviewed-on: https://git-master.nvidia.com/r/1668919
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This patch deals with cleanups meant to make things simpler for the
upcoming os abstraction patches for the sync framework. This patch
causes some substantial changes which are listed out as follows.
1) sync_timeline is moved out of gk20a_fence into struct
nvgpu_channel_linux. New function pointers are created to facilitate os
independent methods for enabling/disabling timeline and are now named
as os_fence_framework. These function pointers are located in the struct
os_channel under struct gk20a.
2) construction of the channel_sync require nvgpu_finalize_poweron_linux()
to be invoked before invocations to nvgpu_init_mm_ce_context(). Hence,
these methods are now moved away from gk20a_finalize_poweron() and
invoked after nvgpu_finalize_poweron_linux().
3) sync_fence creation is now delinked from fence construction and move
to the channel_sync_gk20a's channel_incr methods. These sync_fences are
mainly associated with post_fences.
4) In case userspace requires the sync_fences to be constructed, we
try to obtain an fd before the gk20a_channel_submit_gpfifo() instead of
trying to do that later. This is used to avoid potential after effects
of duplicate work submission due to failure to obtain an unused fd.
JIRA NVGPU-66
Change-Id: I42a3e4e2e692a113b1b36d2b48ab107ae4444dfa
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1678400
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As part of debug session unification following changes are
required.
-Including bug.h header file to fix the compilation issue
on QNX
- The mechanism of posting debug events is OS specific. In Linux
this works through poll fd, wherein we can make use of nvgpu_cond
variables to poll and trigger the corresponding wait_queue
via nvgpu_cond_broadcast_interruptible() call.
The post event functionality on QNX doesn't work on poll though.
It uses iofunc_notify_trigger to post the debug events to calling
process. As such QNX can't work with nvgpu_cond's.
To overcome this issue, it is proposed to create a OS specific
interface for posting debugger events. Linux can call
nvgpu_cond_broadcast_interruptible() in its implementation, which
makes sense since these are already initialized and poll'ed in the
Linux specific code only.
QNX can implement this interface to call iofunc_notify_* functions,
as per its need
Jira VQRM-2363
Change-Id: I0abdc0787f771040b8aff5384290d7e6549f81fb
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Signed-off-by: Prateek Sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1696368
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Currently, hyp_read_ipa_pa_info() only translates IPA for RAM
mappings. It fails for MMIO mappings. In particular, it will
fail when attempting to translate addresses in the syncpoint
shim aperture. As a workaround, assume 1:1 IPA to PA mapping
when hyp_read_ipa_pa_info fails, and address is in syncpt
shim aperture.
Bug 2096877
Change-Id: I5267f0a8febf065157910ad3408374cacd398731
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1687796
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linux driver runs in user's process but qnx driver has dedicate driver
process, so they have different way to get user pid. nvgpu common code
expect calls from os specific code pass pid/tid.
ce/cde open channel for internal use, we use driver pid.
Jira VQRM-3534
Change-Id: I892372ac5f1dc4d25f9928d16992bcc659d12a56
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1694145
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The submit gpfifo flags are splattered everywhere inside the nvgpu
code. Though the usage is inside nvgpu Linux code only, still it
needs to be gotten rid of and replaced with the defines
present in common code.
VQRM-3465
Change-Id: I901b33565b01fa3e1f9ba6698a323c16547a8d3e
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1691979
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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Remove the usage of nvgpu_gpfifo splattered across nvgpu,
and replace with a struct defined in common code.
The usage is still inside Linux, but this helps the
subsequent unification efforts, e.g. to unify the submit
path.
VQRM-3465
Change-Id: I9e5ac697a0c7f85239ddba319085c09481d20d6b
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1691978
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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Remove the usage of nvgpu_fence splattered across nvgpu,
and replace with a struct defined in common code.
The usage is still inside Linux, but this helps the
subsequent unification efforts, e.g. to unify the submit
path.
VQRM-3465
Change-Id: Ic3737450123dfc5e1c40ca5b6b8d8f6b3070aa0d
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1691977
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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- Enabled internal temperature sensor read for gv100
dgpu.
- Added check to temperature read support before
proceeding to read temperature from H/W
- Assigned GP106 temperature HAL's for GV100 as no changes
between GP106 & GV100 H/W registers.
Bug 200352328
Change-Id: I86b5a1859b87ace49a07d0ff3749bb5b085bba91
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1673347
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The pmgr code is in theory common code. However there were uses
of Linux stuff within this code.
This patch cleans that up by deleting the unnecessary os_linux.h
includes, usage of kfree() and adds several platform fields to
the gk20a struct. The platform data is copied to the gk20a struct
in the platform initialization code so that this common code can
access said data without requiring any knowledge of the OS platform
data.
JIRA NVGPU-525
Change-Id: Ic4bb6021f60b0a0778779ab5f3e15b7e5ca98306
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1673825
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The patch defines 'struct nvgpu_gpfifo_args' to be filled
by alloc_gpfifo(_ex) ioctls and passed to the
gk20a_channel_alloc_gpfifo function. This is required as a
prep towards having the usermode submission support in the
core channel core.
Change-Id: I72acc00cc5558dd3623604da7d716bf849f0152c
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1683391
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BIT() is defined as returning a 64-bit value. We use it to create the
log mask values, but the functions that accept log mask take only
u32 as parameter.
Use u64 as log mask parameter for the logging functions to match the
sizes.
Change-Id: I6f0803a7d04ee6a2ee725b5defc4cc14b5b7acf5
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
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When runtime pm is disabled, then gpu rail will be on as soon as
nvgpu module is loaded. If pm suspend/resume called before gpu
hw initialization(g->poweron = false) then pm suspend is skipping
gpu railgate, which is causing issues with SC7 entry/exit.
To fix this issue:
1. During pm suspend, if g->poweron is false, check for runtime pm
disable to railgate gpu rail.
2. On pm resume, check for runtime pm disable to enable gpu rail,
though gpu driver not initialized.
Bug 2073029
Change-Id: I7631109d79cda5882d2864557f1b7b3d2d89c9f6
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
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