3 Commits

Author	SHA1	Message	Date
ajesh	a6cbfca58c	gpu: nvgpu: fix MISRA violations in bitops unit ... Fix the following MISRA rule violations in bitops unit, MISRA Rule 10.1 MISRA Rule 10.3 MISRA Rule 10.4 MISRA Rule 11.8 MISRA Rule 21.2 Introduce nvgpu specific functions for bitops and bitmap operations with unsigned integer as parameter for offset. OS specific type conversions and handling of these inerfaces are taken care in the respective OS files. Jira NVGPU-3545 Change-Id: Ib1ef76563db6ba1d879a0b4d365b2958ea03f85c Signed-off-by: ajesh <akv@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2129513 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-06-11 22:26:41 -07:00
Thomas Fleury	97762279b7	gpu: nvgpu: make nvgpu_init_mutex return void ... Make the nvgpu_init_mutex function return void. In linux case, this doesn't affect anything since mutex_init returns void. For posix, we assert() and die if pthread_mutex_init fails. This alleviates the need to error inject for _every_ nvgpu_mutex_init function in the driver. Jira NVGPU-3476 Change-Id: Ibc801116dc82cdfcedcba2c352785f2640b7d54f Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2130538 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-06-05 10:25:52 -07:00
Sagar Kamble	d7bdca94d8	gpu: nvgpu: move sources to sec2 ipc element ... SEC2 command, message, queues, sequences are part of SEC2's infrastructure for IPC. Create common/sec2/ipc folder and move all these sources there. JIRA NVGPU-2075 Change-Id: Id6d7a31422fae835ec669c8ea48b3f63b9dffe24 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2085756 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-04-10 09:27:42 -07:00