2 Commits

Author	SHA1	Message	Date
Scott Long	89c1ec07b1	gpu: nvgpu: MISRA 11.3 fixes to gr ctx code ... MISRA rule 11.3 states that a cast shall not be performed between a pointer to object type and a pointer to a different object type. The following gr context routines convert a gr context buffer pointer in the form of a u8 * to a u32 * before referencing the context buffer's contents: * gm20b_ctxsw_prog_check_main_image_header_magic * gm20b_ctxsw_prog_check_local_header_magic * gm20b_ctxsw_prog_get_num_gpcs * gm20b_ctxsw_prog_get_num_tpcs * gm20b_ctxsw_prog_get_extended_buffer_size_offset * gm20b_ctxsw_prog_get_ppc_info * gm20b_ctxsw_prog_get_local_priv_register_ctl_offset Because the gr context buffer pointer starts out as a u32 * the conversion to a u8 * isn't strictly necessary. So this patch eliminates the conversion and the 11.3 rule violations accordingly. JIRA NVGPU-782 Change-Id: I0d24b539ad6ee8e56318287ce8640764285ed54d Signed-off-by: Scott Long <scottl@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2102986 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-04-26 02:04:35 -07:00
Deepak Nibade	b429101b90	gpu: nvgpu: move hal.gr.ctxsw_prog unit to hal/ directory ... Move common.hal.gr.ctxsw_prog unit from common/ to hal/ directory since whole unit provides HAL interface only Jira NVGPU-2007 Change-Id: I855e2d4263e7e743c7917620c3a25fe534ba93fe Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2083779 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-03-28 09:26:28 -07:00