3 Commits

Author	SHA1	Message	Date
Seema Khowala	60633ca551	gpu: nvgpu: move gv11b rc code to rc_gv11b.c ... Move chip specific recovery code for volta onwards architecture to hal/rc/rc_gv11b.c Rename fifo.teardown_ch_tsg -> fifo.recover gk20a_runlist_update_locked -> nvgpu_runlist_update_locked Remove Unused h/w headers from fifo_gv11b.c Use local variable f instead of g->fifo JIRA NVGPU-1314 Change-Id: Ia535bbe4780e7241fdd911a8f577c6b98cf0fe53 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2102897 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-04-24 20:23:06 -07:00
Nicolas Benech	0435ca4eb3	gpu: nvgpu: fix MISRA 17.7 in nvgpu.common.hal.fifo.* ... MISRA Rule-17.7 requires the return value of all functions to be used. Fix is either to use the return value or change the function to return void. This patch contains fixes for all 17.7 violations in the following units: - nvgpu.common.hal.fifo.runlist - nvgpu.common.hal.fifo.fifo JIRA NVGPU-3039 Change-Id: I9483f5cb623cfe36d6b26e41c33f124c24710c08 Signed-off-by: Nicolas Benech <nbenech@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2098765 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-04-19 19:04:05 -07:00
Seema Khowala	da9dee85e2	gpu: nvgpu: move mmu fault handling to hal/fifo ... Move chip specific mmu fault handling from fifo_gk20a.c to hal/fifo/mmu_fault_gk20a.c Move gk20a_teardown_ch_tsg to hal/rc/rc_gk20a.c JIRA NVGPU-1314 Change-Id: Idf88b1c312bc9f46c2508f2c63e948d71d622297 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2094051 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-04-18 15:56:08 -07:00