2 Commits

Author	SHA1	Message	Date
Thomas Fleury	2b165deba1	gpu: nvgpu: engines MISRA fixes for Rule 1.1 ... Add missing newline at end of file. Jira NVGPU-3386 Change-Id: Id62f99c1e9517932627949a65fe0b9e4fe802c49 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2113038 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-05-06 14:24:50 -07:00
Debarshi Dutta	61fd020137	gpu: nvgpu: move engine_status and pbdma_status HAL units to hal/fifo ... engine_status and pbdma_status HAL specific units are moved from common/fifo to hal/fifo. Jira NVGPU-1315 Jira NVGPU-2950 Change-Id: Ic4eab71bcc53c04f6b855d5eebe919bce57a3494 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2071271 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-03-21 04:36:48 -07:00