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16 Commits

Author SHA1 Message Date
Antony Clince Alex
68e11c8bd3 gpu: nvgpu: remove nvgpu_next_gpuid.h 
Replace all usages of NVGPU_NEXT_GPUID and NVGPU_NEXT_DGPU_GPUID
with NVGPU_GPUID_GA10B and NVGPU_GPUID_GA100.

Remove nvgpu_next_gpuid.h and update yaml.

Jira NVGPU-4771

Change-Id: I3baf0de4eb5266b79aabd5c6ddf8442bf8f73419
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2547735
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 2021-06-27 05:03:09 -07:00
Antony Clince Alex
c7d43f5292 gpu: nvgpu: remove usage of CONFIG_NVGPU_NEXT 
The CONFIG_NVGPU_NEXT config is no longer required now that ga10b and
ga100 sources have been collapsed. However, the ga100, ga10b sources
are not safety certified, so mark them as NON_FUSA by replacing
CONFIG_NVGPU_NEXT with CONFIG_NVGPU_NON_FUSA.

Move CONFIG_NVGPU_MIG to Makefile.linux.config and enable MIG support
by default on standard build.

Jira NVGPU-4771

Change-Id: Idc5861fe71d9d510766cf242c6858e2faf97d7d0
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2547092
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 2021-06-27 05:02:47 -07:00
Ramesh Mylavarapu
a9a7e4f018 gpu: nvgpu: allocate wpr reserve space for NVRISCV pmu 
Falcon image is cleanly partitioned between a code and
data section where we don't need extra reserved space.
NVRISCV image has no clear partition for code and data
section, so we need reserved wpr space for runtime use.

Bug 200709761

Signed-off-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Change-Id: I80fa89fc10d0a0fd2fb8b74bae499b66d5563e00
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2509553
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-05-04 18:04:30 -07:00
Divya Singhatwaria
6ffadc0e32 gpu: nvgpu: Remove hard coded constants from ACR 
During code inspection use of some hard coded
constants was found in some parts of the code.
Some constants are replaced by macros and some
are declared using const keyword.

JIRA NVGPU-6260

Change-Id: I95112dfcac7c8b996789a68e7ddf78b16713a823
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2485727
(cherry picked from commit b7e554267d9ef94ae5ac4529f4758127b97d3ba5)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2492451
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Andrey Jivsov <ajivsov@nvidia.com>
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 2021-03-27 04:57:37 -07:00
ajesh
0030dc3eb4 gpu: nvgpu: fix MISRA violations in Posix unit 
Fix violations of MISRA rule 5.4 in Posix unit.

JIRA NVGPU-6534

Change-Id: I9471e5fca913ca8cc19403998fdbe5450fb49879
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2488184
(cherry picked from commit f9bc21ca8d96e9c531a1b0077cfe1e78502e7ee5)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2491855
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 2021-03-04 00:37:15 -08:00
mkumbar
65111b64f2 gpu: nvgpu: Add RISCV LS PMU support 
-Add RISCV LS PMU support by adding RISCV LS PMU ucode to the blob.
-Modify the PMU RTOS sequence based on NEXT CORE enable flag.

JIRA NVGPU-6303

Change-Id: I4e2b989f9903b72a6327c931eb3c02f8cef2aa75
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2447388
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GVS: Gerrit_Virtual_Submit
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 2020-12-17 18:36:44 -06:00
mkumbar
be6b37ba50 gpu: nvgpu: add support for ls_falcon_ucode_desc_v1 
igpu-next LSPMU ucode built with newer ucode descriptor which adds
changes to ACR blob construction.
Constructing ACR blob with legacy ucode descriptor by fetching required
data from ucode using newer descriptor.

JIRA NVGPU-5857

Change-Id: I6d830be1ec955242b95f522e648528a6b36e7cf5
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2382855
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 2020-12-15 14:13:28 -06:00
mkumbar
8fbc4e5b56 gpu: nvgpu: update ACR sub-wpr support 
update ACR sub-wpr support by deleting FRTS_VBIOS_TABLES
sub-wpr id support.
FRTS_VBIOS_TABLES sub-wpr causing NEXT dGPU ACR AHESASC
to hit ACR_ERROR_FLCN_ID_NOT_FOUND error and these tables
are not supported by NVGPU.

JIRA NVGPU-5462

Change-Id: I2de20b27a1a3ecbf4b3acb793eb22c637c4faba6
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2368213
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 2020-12-15 14:13:28 -06:00
smadhavan
c261f7573b gpu: nvgpu: support nvgpu-next secure boot 
Add NVGPU_NEXT_GPUID in
nvgpu_acr_init, nvgpu_acr_lsf_fecs_ucode_details,
and nvgpu_acr_lsf_gpccs_ucode_details functions.

JIRA NVGPU-5323

Change-Id: I514ab6de08ffaad323072499a92acef24668d3fc
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2361630
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
mkumbar
4b206055ae gpu: nvgpu: Move SEC2 RTOS ucode to last in the WPR blob 
-This change is required to have reduced access of WPR1 region
for ACRLIB hosting falcon.
-By doing the above we allow only L3 Read access for ACRLIB
hosting falcon, enforcing better security.
-Fixed freeing of ACR resource at exit upon failure.

JIRA NVGPU-5459

Change-Id: I9c32a1fe723570cf3768f7e741a7a2e9d96cc1bf
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2365589
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 2020-12-15 14:13:28 -06:00
mkumbar
c43e3e4aeb gpu: nvgpu: acr: add fecs/gpccs sig files read for next dgpu 
add fecs/gpccs sig file read for next dgpu.

JIRA NVGPU-5461

Change-Id: Ib135dab8961c53d62fb7a95e378eba4c81d729a2
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2354622
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 2020-12-15 14:13:28 -06:00
Divya Singhatwaria
1f6dfb54d1 gpu: nvgpu: Remove hard coded constants from ACR 
During code inspection use of some hard constants was
found in some parts of the code.
Those constants are replaced by macros

JIRA NVGPU-5030

Change-Id: I09212be40746317440218bc7ada9a578dde7c6ed
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2301596
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Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Scott Long
20114c7c8c gpu: nvgpu: acr: misra 12.1 fixes 
MISRA Advisory Rule states that the precedence of operators within
expressions should be made explicit.

This change removes the Advisory Rule 12.1 violations from acr code.

Jira NVGPU-3178

Change-Id: Ibfcb23dbf9931efd1890c9b548c36462c55ae47d
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2277477
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 2020-12-15 14:10:29 -06:00
Divya Singhatwaria
8592b0591c gpu: nvgpu: Add fail scenarios in ACR unit tests 
- Add more fail scenarios in ACR unit tests to cover
  branches
- Return "err" value when "get_lsf_ucode_details" ops
  for fecs fails.

JIRA NVGPU-4319

Change-Id: Ic9ba0afb26b23f6e0c0ebd76feae5b1ba3098b93
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2252801
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 2020-12-15 14:10:29 -06:00
Mahantesh Kumbar
cb63f7db2f gpu: nvgpu: Moved NVGPU-ACR interfaces to separate file 
-Moved NVGPU-ACR interfaces to separate header file from
 ACR blob/bootstrap header files.
-Separation needed for NVGPU-ACR interface specification
 doxygen.

JIRA NVGPU-4152

Change-Id: Ia502380e62f53e0372549544e31ffff150e05017
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2219038
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 2020-12-15 14:10:29 -06:00
Mahantesh Kumbar
fbf219d8ba gpu: nvgpu: ACR func/struct version update for FUSA 
-Renamed ACR structs for FUSA, ACR FUSA code has struct names
 ending with _v1 & ACR non-FUSA with _v0, removed _v1 for FUSA
 code to keep struct without any versioning for doxygen.
-Renamed acr_blob_construct_v1.c/h to  acr_blob_construct.c/h

JIRA NVGPU-2516

Change-Id: Id2d5e48e8169ce59371c2b08d04c5a65ba94c685
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2218265
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 2020-12-15 14:10:29 -06:00