Commit Graph

4 Commits

Author SHA1 Message Date
Deepak Nibade
27b321e1a9 gpu: nvgpu: fix header guards in common.gr unit
Fix header guard names as per convention for below common.gr headers :
common/gr/gr_falcon_priv.h
common/gr/zbc_priv.h
include/nvgpu/gr/ctx.h

Jira NVGPU-5005

Change-Id: I68947ea3e8f4ddbcd43be8d8717eb8ddcc6f5bcb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2470072
(cherry picked from commit eb044acbafc6d9f735e066d9c7497156f1df13c7)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2478884
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2021-02-02 23:34:21 -08:00
Vedashree Vidwans
94bc3a8135 gpu: nvgpu: rearch zbc code and update hals
Update nvgpu_gr_zbc as:
struct nvgpu_gr_zbc {
   struct nvgpu_mutex zbc_lock;	/* Lock to access zbc table */
   struct zbc_color_table *zbc_col_tbl; /* SW zbc color table pointer */
   struct zbc_depth_table *zbc_dep_tbl; /* SW zbc depth table pointer */
   struct zbc_stencil_table *zbc_s_tbl; /* SW zbc stencil table pointer */
   u32 min_color_index;	/* Minimum valid color table index */
   u32 min_depth_index;	/* Minimum valid depth table index */
   u32 min_stencil_index;	/* Minimum valid stencil table index */
   u32 max_color_index;	/* Maximum valid color table index */
   u32 max_depth_index;	/* Maximum valid depth table index */
   u32 max_stencil_index;	/* Maximum valid stencil table index */
   u32 max_used_color_index; /* Max used color table index */
   u32 max_used_depth_index; /* Max used depth table index */
   u32 max_used_stencil_index; /* Max used stencil table index */
};

Add global struct nvgpu_gr_zbc_table_indices
struct nvgpu_gr_zbc_table_indices {
       u32 min_color_index;
       u32 min_depth_index;
       u32 min_stencil_index;
       u32 max_color_index;
       u32 max_depth_index;
       u32 max_stencil_index;
};

Currently, hw zbc table registers are written during both
gr_init_setup_sw() and gr_init_setup_hw().
- Modify nvgpu_gr_zbc_load_default_table() to
nvgpu_gr_zbc_load_default_sw_table() to only update sw copy of zbc table
during gr_init_setup_sw().
- Modify nvgpu_gr_zbc_load_table() to write zbc values stored in sw zbc
table to hw registers.

Re-structure zbc function as per zbc type i.e. color, depth and stencil.

Add gr.zbc.init_table_indices() hal to initialize zbc indices. Valid ZBC
table indices start from 1. HW indices start from 0 for color, depth and
stencil tables. Note that the corresponding format registers follow ZBC
index range starting at 1.
- void (*init_table_indices)(struct gk20a *g,
	struct nvgpu_gr_zbc_table_indices *zbc_indices);
- Add corresponding functions for legacy chips
- Add zbc color, depth and stencil table size hw defines
- Remove ltc.zbc_table_size() hal
- Update ltc.set_zbc_s_entry(), ltc.set_zbc_color_entry and
ltc.set_zbc_depth_entry() accordingly.

Bug 3122410
Bug 3122649

Change-Id: Ib799991ad35c6613534c0a6eb07f3bf24e600dc5
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2417620
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2020-12-15 14:13:28 -06:00
Nitin Kumbhar
1a843ba051 gpu: nvpgu: move zbc structs to priv header
Move nvgpu_gr_zbc_entry and nvgpu_gr_zbc to a priv header and
add APIs to access members of those structs.

JIRA NVGPU-3060

Change-Id: I1255f3ebda03f599aed3706136c0909491023067
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2091214
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2019-04-08 01:55:33 -07:00
Vinod G
bbb0caa42c gpu: nvgpu: rearrange gr/zbc files
move zbc hal files from common/gr/zbc to hal/gr/zbc directory.
rename gr/zbc/gr_zbc.c -> gr/zbc.c and gr/zbc/gr_zbc.h -> gr/zbc_priv.h

JIRA NVGPU-1882

Change-Id: I58c98c0a494b600a35a576a9d717114023118ee6
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2071962
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2019-03-15 12:14:42 -07:00