Currently, we are performing obj ctx alloction for bellow classes
1. VOLTA_COMPUTE_A
2. VOLTA_DMA_COPY_A
3. VOLTA_CHANNEL_GPFIFO_A
In safety, we use Async CE but not GRCE.
So allocating obj context only for COMPUTE_A and return success(0) for
all other valid classes, after setting class in the channel struct.
Jira NVGPU-4378
Change-Id: Ie99872e062cc66f9ddf699397a13df85c3d8d59e
Signed-off-by: sagar <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2287486
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Currently, size of zbc index table is defined as a macro. This macro is
independent of the number of address bits in the ltc zbc index register.
Adding below hal will update zbc index table size as per number of
address bits.
Add hal to get gr_zbc_index_table_size:
u32 (*zbc_table_size)(struct gk20a *g);
ZBC index table address 0 is reserved. Logic to start zbc table index
from 1 is moved to corresponding hals.
JIRA NVGPU-4838
Change-Id: I700cadfdd1f3dc5f323055b8f44d769d6627920a
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2288479
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Below functions in common.gr.obj_ctx subunit include unnecessary
asserts to ensure value is not truncated when parsing into U32 size.
nvgpu_gr_obj_ctx_gr_ctx_alloc()
Make use of nvgpu_safe_cast_u64_to_u32() and remove unnecessary
asserts
Jira NVGPU-4778
Change-Id: Ic06c2f4131b3bba35222f7de5441f82ecee6d83d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2277158
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To achieve permanent fault coverage, the CTAs launched by
each kernel in the mission and redundant contexts must execute on
different hardware resources. This feature proposes modifications
in the software to modify the virtual SM id to TPC mapping across
the mission and redundant contexts. The virtual SM identifier to TPC
mapping is done by nvgpu when setting up the patch context.
The recommendation for the redundant setting is to offset the
assignment by one TPC, and not by one GPC. This will ensure that both
GPC and TPC diversity. The SM and Quadrant diversity will happen
naturally. For kernels with few CTAs, the diversity is guaranteed
to be 100%. In case of completely random CTA allocation,
e.g. large number of CTAs in the waiting queue, the diversity is
1 - 1/#SM, or 87.5% for GV11B, 97.9% for TU104.
Added NvGpu CFLAGS to enable/disable the SM diversity support
"CONFIG_NVGPU_SM_DIVERSITY".
This support is only enabled on gv11b and tu104 QNX non safety build.
JIRA NVGPU-4685
Change-Id: I8e3eaa72d8cf7aff97f61e4c2abd10b2afe0fe8b
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2268026
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Add new unit test to cover gops.gr.init.ecc_scrub_reg HAL function
gops.gr.init.ecc_scrub_reg HAL can generate TIMEOUT errors which are
not returned to caller currently. Update this HAL to return int value
for error propagation.
Jira NVGPU-4458
Change-Id: I98f4d5af2ef17cc4301951fec4d660638c8ef72c
Signed-off-by: dnibade <dnibade@nvidia.com>
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Add negative tests that inject memory allocation failures and
HAL function call errors to verify error handling path in
common.gr.obj_ctx unit.
Update common.gr.setup test to cover invalid class input while
setting preemption mode.
Jira NVGPU-4457
Change-Id: I74d1ba63ba8aace6087b51fd50e2c136822d3a00
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2260939
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- nvgpu_gr_ctx_load_golden_ctx_image() does not return any error, change
the return type to void
- Check for preemption modes greater than CILP in
nvgpu_gr_ctx_check_valid_preemption_mode
- Check if received class is valid or not in
nvgpu_gr_setup_set_preemption_mode
- Compile out entire nvgpu_gr_obj_ctx_init_ctxsw_preemption_mode since
it is really not doing anything in safety
- Remove the switch statement in nvgpu_gr_obj_ctx_set_compute_preemption_mode
since it is not possible to receive any other value than supported.
Previous function calls ensure that input values are validated.
- nvgpu_gr_obj_ctx_commit_global_ctx_buffers() does not return any
error, change the return type to void
- gops.gr.init.preemption_state HAL is not needed in safety since it
only configures gfxp related timeout
- remove redundant call to gops.gr.init.wait_idle in
nvgpu_gr_obj_ctx_commit_hw_state. We trigger wait despite earlier
failure in same function call.
Jira NVGPU-4457
Change-Id: I06a474ef7cc1b16fbc3846e0cad1cda6bb2bf2af
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2260938
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Split GR ECC initialization into GPC/TPC and FECS ECC init as FECS ECC
errors during acr_construct_execute need to be reported and handled
hence FECS ECC counters are required to be initialized before
acr_construct_execute.
GPC/TPC ECC counters are dependent on the GR config that will be
initialized only after acr_construct_execute.
nvgpu_gr_intr_init_support is moved to nvgpu_gr_prepare_sw.
FECS ECC interrupt is enabled by default hence interrupt is not
enabled through gr_fecs_host_int_enable_r in nvgpu_gr_prepare_sw.
JIRA NVGPU-4439
Change-Id: Ifc9912f0578015a6ba1e9d38765c42633632b15f
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2261987
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Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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get_gpc_mask hal is set only for tu104. Add CONFIG_NVGPU_DGPU check
in the code for using that hal.
gr_config_alloc_struct_mem function is called from nvgpu_gr_config_init
gr_config_free_mem is called gr_config_alloc_struct_mem on failure.
No need to call gr_config_free_mem from nvgpu_gr_config_init again
for failure.
nvgpu_gr_config_init allocate nvgpu_gr_config struct.
config->sm_to_cluster will never get allocated before.So no need to
check for config->sm_to_cluster and do a memset.
Jira NVGPU-4531
Change-Id: I928041c110019bec885f9d5b6978db3032bc493c
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2262229
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handle_tex_exception hal is not set for safety build. Add
CONFIG_NVGPU_HAL_NON_FUSA checking for that hal.
log_mme_exception hal is supported only for turing. Add
CONFIG_NVGPU_DGPU checking for that hal.
gr_intr_handle_class_error always return -EINVAL. Change the
return as void to avoid unwanted error checking.
nvgpu_gr_intr_get_channel_from_ctx function parameter curr_tsgid will
never be NULL based on the current call. Remove unwanted
(curr_tsgid != NULL) check from this function.
Jira NVGPU-4454
Change-Id: I165d1cc5f9e308dfb11d905b59151b44f63a31bb
Signed-off-by: vinodg <vinodg@nvidia.com>
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- Set ENOMEM error if GPU mapping fails in nvgpu_gr_ctx_alloc().
- In nvgpu_gr_ctx_free_patch_ctx(), it is not possible to have a
valid patch buffer without GPU virtual address space. Hence instead
of checking for gpu_va, use nvgpu_mem_is_valid() to check if GPU
mappings can be removed.
- Check if RTV circular buffer is ready within DGPU config.
nvgpu_gr_global_ctx_buffer_map() already checks if buffer is ready
or not and returns error if buffer is not ready.
- g->ops.gr.ctxsw_prog.init_ctxsw_hdr_data() will always be set for
each chip. Remove unnecessary NULL check.
Jira NVGPU-4373
Change-Id: Ib490f81f8b8299f87cffbb8a33fde8cf98e6c288
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2259073
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In nvgpu_gr_setup_set_preemption_mode function, nvgpu_channel_enable_tsg
and nvgpu_channel_disable_tsg calls are changed to gops calls.
In this function beginning nvgpu_tsg_from_ch is checked for NULL pointer
so nvgpu_channel_enable_tsg and nvgpu_channel_disable_tsg functions
never fail with NULL tsg pointer for branch coverage.
Jira NVGPU-3968
Change-Id: If2e1fee493426e56d62865b015dc8b21bad494b6
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2258788
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* Updated types and added error checks
* Modified GR condition for ctxsw disable count
CERT-C error check was added to detect error on integer overflow
But below logic couldn't detect first overflow, so updated condition
INT_MAX < gr->ctxsw_disable_count --> it became true after overflow
So, we didn't detected in first overflow and lead to assert on enable
JIRA NVGPU-3400
Change-Id: I6b0265a464f8f19efa7b0761612c6e9ffb3bd2bd
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2206282
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HAL gops.gr.config.init_sm_id_table() initializes SM count in struct
nvgpu_gr_config. It is almost impossible that SM count is detected as
zero.
Hence remove the error check and add an assert instead.
This also helps with code coverage tests since it is difficult to
simulate error condition of having zero SMs detected.
Also, HAL gops.gr.config.init_sm_id_table() should always be defined
for each platform. Hence remove unnecessary check.
Jira NVGPU-4373
Change-Id: Ibd9b301b28d5bd2952367346a8f12fabcee2abd9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2247845
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FECS ucode introduces separate register lists for control registers, so
that they can be restored separately from PM state.
Added support for:
- LIST_compressed_nv_perf_sys_control_ctx_regs
- LIST_compressed_nv_perf_pma_control_ctx_regs
- LIST_compressed_nv_perf_fbp_control_ctx_regs
- LIST_compressed_nv_perf_gpc_control_ctx_regs
Bug 200507276
Change-Id: Ifce398bcb298822f3a46cf372ef9610a46a8df0c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
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Move code used only with graphics under
CONFIG_NVGPU_GRAPHICS check.
gm20b_gr_init_load_sw_bundle_init hal get called
without CONFIG_NVGPU_GR_GOLDEN_CTX_VERIFICATION check.
Remove dead code in
nvgpu_gr_ctx_check_valid_preemption_mode function.
Jira NVGPU-3968
Change-Id: I399126123006ae44dba29b3c08378d11fe82e543
Signed-off-by: vinodg <vinodg@nvidia.com>
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Previously, unit interrupt enabling/disabling and corresponding MC level
interrupt enabling/disabling was not done at the same time.
With this change, stall and nonstall interrupt for units are programmed
at MC level along with individual unit interrupts. Kept access to MC
interrupt registers through mc.intr_lock spinlock.
For doing this separated CE and GR interrupt mask functions.
mc.intr_enable is only used when there is global interrupt
control to be set. Removed mc_gp10b.c as mc_gp10b_intr_enable
is now removed. Removed following functions - mc_gv100_intr_enable,
mc_gv11b_intr_enable & intr_tu104_enable. Removed intr_pmu_unit_config
as we can use the generic unit interrupt control function.
JIRA NVGPU-4336
Change-Id: Ibd296d4a60fda6ba930f18f518ee56ab3f9dacad
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
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To enable ecc interrupts early during nvgpu_finalize_poweron, ecc
support has to be enabled early. ecc support was being initialized
together for GR, LTC, PMU, FB units late in the poweron sequence.
Move the ecc init for each unit to respective unit's init functions.
And separate out the hal ecc functions from GR ecc unit to
respective hal units.
JIRA NVGPU-4336
Change-Id: I2c42fb6ba3192dece00be61411c64a56ce16740a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2239153
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Typically, the PMU init thread will finish up long
before the golden context image has been initialized,
which means that ELPG hasn't truly been enabled at that
point.
Create a new function, nvgpu_pmu_reenable_pg(), which
checks if elpg had been enabled (non-zero refcnt), and
if so, disables then re-enables it.
Call this function from nvgpu_gr_obj_ctx_alloc() after
the golden context image has been initialized to ensure
that elpg is truly enabled.
Bug 200543218
Change-Id: I0e7c4f64434c5e356829581950edce61cc88882a
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
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Move graphics related defs and functions under CONFIG_NVGPU_GRAPHICS
switch.
Move classes not supported in GV11B under CONFIG_NVGPU_NON_FUSA
switch.
Add missing valid class numbers to gpu_class.is_valid HAL.
Also remove un-used class defs from class.h header.
Lot of qnx safety tests are still using graphics 3d class.
Until those tests got fixed, allowing 3d graphics class
as valid class for safety build.
JIRA NVGPU-4301
Change-Id: Ifd2a13bee3210821799c2bca10e7245eb3c79121
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
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gk20a.h will include gops_mc.h to contain the mc ops definitions. Add
doxygen comments for the HAL functions that are called directly.
Also move mc_gp10b_intr_pmu_unit_config to non-fusa HAL file.
JIRA NVGPU-2524
Change-Id: I4f326332d7842211b004b372d79fac9fe6ed40e7
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
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Update struct nvgpu_fecs_ecc_status comments for doxygen.
Move structures for method, mailbox and cond outside
the nvgpu_fecs_method_op struct, for better doxygen
format. Defining sturct within struct doesnot look
good in doxygen.
Jira NVGPU-4107
Change-Id: I34b2249119e5578c568139f958e6edab9d75d7c8
Signed-off-by: Vinod G <vinodg@nvidia.com>
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nvgpu.common.unit was just an enum used for passing to nvgpu.common.mc
APIs. So, move the enum into mc.h, and replace the include of unit.h
with mc.h where appropriate. And update the yaml arch.
JIRA NVGPU-4144
Change-Id: I210ea4d3b49cd494e43add1b52f3fbcdb020a1e3
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2216106
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Add doxygen documentation for private GR structures defined in:
gr/gr_config_priv.h
gr/gr_falcon_priv.h
gr/gr_intr_priv.h
gr/gr_priv.h
Remove "p_va" field from struct nvgpu_ctxsw_ucode_info since it is
unused.
Compile out "pm_ctxsw_image_size" with flag CONFIG_NVGPU_DEBUGGER.
Compile out "preempt_image_size" with flag CONFIG_NVGPU_GRAPHICS.
Replace eUcodeHandshakeInitComplete enum value by macro
FALCON_UCODE_HANDSHAKE_INIT_COMPLETE. And remove enum value
eUcodeHandshakeMethodFinished since it is unused.
Compile "ctxsw_disable_mutex" and "ctxsw_disable_count" in struct
nvgpu_gr only if CONFIG_NVGPU_RECOVERY or CONFIG_NVGPU_DEBUGGER is
defined
Jira NVGPU-4028
Change-Id: Ie8769c1f3f8d313b479b182d3858a6715d49cd4c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
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