3 Commits

Author	SHA1	Message	Date
Vedashree Vidwans	86cb03d2f1	gpu: nvgpu: Replace WAR keyword with "fix" ... Replace/remove "WAR" keyword in the comments in nvgpu driver with "fix". Rename below functions and corresponding gops to replace "war" word with "errata" word: - g.pdb_cache_war_mem - ramin.init_pdb_cache_war - ramin.deinit_pdb_cache_war - tu104_ramin_init_pdb_cache_war - tu104_ramin_deinit_pdb_cache_war - fb.apply_pdb_cache_war - tu104_fb_apply_pdb_cache_war - nvgpu_init_mm_pdb_cache_war - nvlink.set_sw_war - gv100_nvlink_set_sw_war Jira NVGPU-6680 Change-Id: Ieaad2441fac87e4544eddbca3624b82076b2ee73 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2515700 Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit	2021-04-28 19:14:49 -07:00
Antony Clince Alex	c36752fe3d	gpu: nvgpu: sim: make ring buffer independent of PAGE_SIZE ... The simulator ring buffer DMA interface supports buffers of the following sizes: 4, 8, 12 and 16K. At present, it is configured to 4K and it happens to match with the kernel PAGE_SIZE, which is used to wrap back the GET/PUT pointers once 4K is reached. However, this is not always true; for instance, take 64K pages. Hence, replace PAGE_SIZE with SIM_BFR_SIZE. Introduce macro NVGPU_CPU_PAGE_SIZE which aliases to PAGE_SIZE and replace latter with former. Bug 200658101 Jira NVGPU-6018 Change-Id: I83cc62b87291734015c51f3e5a98173549e065de Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2420728 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>	2020-12-15 14:13:28 -06:00
Thomas Fleury	0e1e142aa9	gpu: nvgpu: move pdb_cache_war to ramin HAL ... Removed dependency on ram tu104 hw header from fifo code. Moved the following HALs from fifo to ramin - init_pdb_cache_war - deinit_pdb_cache_war Jira NVGPU-2012 Change-Id: Ia1848c430b8d19861d92d14d3cd01c9119553002 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2105351 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-04-26 12:04:03 -07:00