CIC (Central Interrupt controller) will be responsible for the
interrupt handling. common.cic unit is the placeholder for all
interrupt related code. Move interrupt related defines and
Public APIs present in common.mc to common.cic.
Note: The common.mc interrupts related struct definitions are
not moved as part of this patch.
Adapt the code to use interrupt handling related defines and public
APIs migrated from common.mc to common.cic
JIRA NVGPU-6899
Change-Id: I747e2b556c0dd66d58d74ee5bb36768b9370d276
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2535618
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This is adding fix for dev_node leak when user_deinit
called.
The dev_nodes in linux are created in two phases. In first
phase the power dev_nodes(one for legacy and other for v2)
are created. The second phase other dev_nodes are created.
While creating the dev_nodes the power cdev_region overwritten
by cdev_region. This is fixed by introducing new cdev_region and
updating respective nodes.
JIRA NVGPU-6721
Change-Id: Iec78db8e5fe40cc0b14fb3fecc35b8881dff716f
Signed-off-by: dt <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2535265
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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Fixes:
1) gk20a_sched_dev_ioctl allocates a buffer with size
*CTXSW_IOCTL_MAX_ARG_SIZE* but then sanitizes IOC_SIZE
against *SCHED_IOCTL_MAX_ARG_SIZE*. No big deal here
since both are of size 0x20 but may lead to issues in
the future.
2) nvgpu_clk_arb_ioctl_event_dev would BUG_ON if IOC_SIZE
is larger than expected. Let's instead sanitize and return
error.
Jira VFND-1586
Jira VQRM-3741
Change-Id: I9e00796a2b2f4a83c3a04194c34eb4c006b937d3
Signed-off-by: Martin Radev <mradev@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2525753
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
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Add a new Central Interrupt Controller(CIC) unit in common code.
The interrupt handling is done in a distributed manner currently.
The error handling policy for different errors resides in each unit's
ISR code. The goal is to converge this data under one central place -
the CIC unit.
This patch creates framework for CIC unit and moves the gv11b QNX
safety LUT to CIC unit. All the error reporting APIs from different
units are also moved to CIC.
New APIs are exposed by CIC unit to access its internal data like:
1. Struct err_desc - the static err handling /injection data per
error id
2. Num_hw_modules - the number of error reporting HW units
supported by CIC
Init and deinit of CIC unit:
1. CIC unit should be initialized earlyon during boot so that it
is available for any interrupt handling.
2. Initialize CIC just before the interrupts are enabled during
boot.
3. Similarly, CIC is disabled late during deinit cycle; right
after the interrupts are masked.
LUT:
1. LUT is currently used only for reporting error to safety
services in gv11b QNX safety build.
2. This error handling policy LUT currently has only two levels
of handing - correctable and quiecse.
3. Once, the error handling policy decision is moved from leaf
unit nodes to CIC, LUT will be updated to have additional levels
like fast recovery and full recovery.
4. Also, then a separate LUT will be added for each platform/build.
5. In current framework, the LUT is set to NULL for all
configurations except gv11b.
report_err() ops is added to report error to safety services.
This ops is only effective for gv11b qnx build; and set to NULL for
other configurations.
NVGPU-6521
NVGPU-6523
NVGPU-6750
NVGPU-6758
NVGPU-6760
NVGPU-6754
Change-Id: I24be7836a96d787741e37b732e19863ed8014635
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2518683
Reviewed-by: Ajesh K V <akv@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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This is adding code to select MIG mode and boot
the GPU with selected mig config.
For testing MIG, after system boots
1. write mig_mode_config by
echo x > /sys/devices/gpu.0/mig_mode_config for igpu
echo x > /sys/devices/./platform/14100000.pcie/pci0001:00/0001:00:00.0/0001:01:00.0/ for dgpu
2. Then run any nvgpu* tests or nvrm_gpu_info.
If the mig_mode need to be changed , note down the supported
configs by "cat mig_mode_config_list" and reboot the system
3. Follow steps 1 and 2.
example output:
"cat mig_mode_config" 2
"cat mig_mode_config_list"
+++++++++ Config list Start ++++++++++
CONFIG_ID : 0 for CONFIG NAME : 2 GPU instances each with 4 GPCs
CONFIG_ID : 1 for CONFIG NAME : 4 GPU instances each with 2 GPCs
CONFIG_ID : 2 for CONFIG NAME : 7 GPU instances - 1 GPU instance with 2
GPCs + 6 GPU instances each with 1 GPC
CONFIG_ID : 3 for CONFIG NAME : 5 GPU instances - 1 GPU instance with 4
GPCs + 4 GPU instances each with 1 GPC
CONFIG_ID : 4 for CONFIG NAME : 4 GPU instances - 1 GPU instance with 2
GPCs + 2 GPU instances each with 1 GPC + 1 GPU instance with 4 GPCs
CONFIG_ID : 5 for CONFIG NAME : 6 GPU instances - 2 GPU instances each
with 2 GPCs + 4 GPU instances each with 1 GPC
CONFIG_ID : 6 for CONFIG NAME : 5 GPU instances - 1 GPU instance with
2 GPCs + 2 GPU instances each with 1 GPC + 2 GPU instances with 2 GPCs
CONFIG_ID : 7 for CONFIG NAME : 5 GPU instances - 2 GPU instances each
with 2 GPCs + 1 GPC instance with 2 GPCs + 2 GPU instances with 1 GPC
CONFIG_ID : 8 for CONFIG NAME : 5 GPU instances - 1 GPC instance with 2
GPCs + 2 GPU instances each with 1 GPC + 2 GPU instances each with 2
GPCs
CONFIG_ID : 9 for CONFIG NAME : 1 GPU instance with 8 GPCs
++++++++++ Config list End +++++++++++
JIRA NVGPU-6633
Change-Id: I3e56f8c836e1ced8753a60f328da63916faa7696
Signed-off-by: dt <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2522821
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- The power device node is created at bootime and the power node
is used to power-on the GPU. Power node is commmon for MIG and
non-MIG platforms. As the same API is used for power and
other MIG/non-MIG nodes, we need to distinguish between them.
Otherwise the same nodes creation will give boot issue.
- As we are supporting mig_mode setting for non-mig platforms
like GV11B, the condition need to be added to create MIG-modes
or not. If any mig-mode is set on gv11b/tu104 then graphics pipeline
will be disabled.
JIRA NVGPU-6633
Signed-off-by: dt <dt@nvidia.com>
Change-Id: I3c641e50c39180543efff04a9cf8b721dbf7f648
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2521732
Reviewed-by: svcacv <svcacv@nvidia.com>
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Currently, there are few chip specific erratas present in nvgpu code.
For better traceability of the erratas and corresponding fixes,
introduce flags to indicate existing erratas on a chip. These flags
decide if a corresponding solution is applied to the chip(s).
This patch introduces below functions to handle errata flags:
- nvgpu_init_errata_flags
- nvgpu_set_errata
- nvgpu_is_errata_present
- nvgpu_print_errata_flags
- nvgpu_free_errata_flags
nvgpu_print_errata_flags: print below details of erratas present in chip
1. errata flag name
2. chip where the errata was first discovered
3. short description of the errata
Flags corresponding to erratas present in a chip are set during chip hal
init sequence.
JIRA NVGPU-6510
Change-Id: Id5a8fb627222ac0a585aba071af052950f4de965
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2498095
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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The function nvgpu_pci_probe invokes nvgpu_kzalloc(g) with a pointer
to struct gk20a before setting the device pointer in struct
nvgpu_os_linux. This may result in NULL Pointer access in the function
nvgpu_log_name when some logs are enabled during boot.
As a solution, the implementation of nvgpu_log_name is updated to first
check for a valid pointer to a struct device before calling dev_name
Jira NVGPU-6770
Change-Id: I98a9746550e43f3b7a143f5b7c7141ff6c67f758
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2520355
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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1) NvGpu dev node needs to be created in gpu power on
early stage to avoid latency introduced by udevd.
For creating dev node, device and grmgr init
needs to move to early stage of GPU power on.
After grmgr init, NvGpu can identify the number of MIG
instance required for each physical GPU.
For that, added a new API nvgpu_early_poweron() to handle
early init which is required for before dev node creation.
2) Removed fifo dependency in nvgpu_init_gr_manager()
3) Used get_max_subctx_count() directly to query
the veid/subctx count.
JIRA NVGPU-6633
Change-Id: Ib9d7c3e184c71237b0da9305515ccd8ceda1d5ad
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2517173
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This is adding two sysfs nodes
1. mig_mode_config: to select the mig_mode
2. mig_mode_config_list: to list the available mig configs.
Added logic to skip gpu dev node creation only for
real MIG physical device.
Added logic to skip the gpu characteristics flags only for
real MIG physical device.
JIRA NVGPU-6633
Change-Id: I4a450b6d658f76e79d89f863c00dffad4558c70f
Signed-off-by: dt <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2499284
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- This is deferring the dev_nodes creation after power_on to
select the MIG config and to create the dev_nodes as per the
selected MIG config.
- The patch is adding a device node to issue power on. The
nodes are:
for igpu :/dev/nvgpu/igpu0/power
for dgpu:/dev/nvgpu/dgpu-0001:01:00.0/power
To issue power on :
echo "1" > /dev/nvgpu/igpu0/power
echo "1" > /dev/nvgpu/dgpu-0001:01:00.0/power
JIRA NVGPU-6633
Change-Id: Ic4f1f3e42724cc788dcfaf0e881d188fd3bd1ce1
Signed-off-by: dt <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2512647
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- moved reg fields to gk20a
- added os abstract register accessor in nvgpu/io.h
- defined linux register access abstract implementation
- hook up with posix. posix implementation of the register accessor uses
the high 4 bit of address to identify register apertures then call the
according callbacks.
It helps to unify code across OSes.
Bug 2999617
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: Ifcb737e4b4d5b1d8bae310ae50b1ce0aa04f750c
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2497937
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Introduce new HAL gops_ltc.set_l2_sector_promotion to configure L2
sector promotion policy. The follow three promotion settings are support:
- NVGPU_GPU_IOCTL_TSG_L2_SECTOR_PROMOTE_FLAG_NONE
- NVGPU_GPU_IOCTL_TSG_L2_SECTOR_PROMOTE_FLAG_64B
- NVGPU_GPU_IOCTL_TSG_L2_SECTOR_PROMOTE_FLAG_128B
Add ioctl "NVGPU_TSG_IOCTL_SET_L2_SECTOR_PROMOTION" to the gpu tsg node
to support l2 sector promotion. On chips which do not support sector
promotion, the ioctl returns 0.
Bug 200656177
Change-Id: Iad835a5c954d3b10da436cfafb388aaaa04f44c7
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2460553
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This is one of the steps in restructuring of interrupt code.
- Move ISR logic to common code. This will allow us to add mixed ASIL
error handling levels.
- Modify nonstall ISR to use threaded interrupts. Bottom half of
nonstall ISR will run nonstall operations instead of adding work to
workqueues.
- Remove nonstall workqueue implementation.
JIRA NVGPU-6351
Change-Id: I5f891b0de4b0c34f6ac05522a5da08dc36221aa6
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2467713
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Add new NVGPU_SUPPORT_MAPPING_MODIFY enable flag that is used to
control the value of the exported NVGPU_GPU_FLAGS_SUPPORT_MAPPING_MODIFY
flag.
These flags are currently only enabled on linux in non-virtualized
environments.
Jira NVGPU-6374
Change-Id: Ia85c353b767b4f7d0aebc04838f44996bc38c61f
Signed-off-by: scottl <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2490986
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Add ioctl support to configure and read the max number of lines/ways
in a L2 cache set that can be marked as EVICT_LAST. This is accomplished
through two new ltc hals: set_l2_max_ways_evict_last,
get_l2_max_ways_evict_last. These hals will only be set for nvgpu-next
chips. Incase of legacy chips, the IOCTLs will return error -ENOSYS.
Generate following litter constants to get the number of sets in a l2
slice and the number of ways in each set:
- GPU_LIT_NUM_LTC_LTS_SETS
- GPU_LIT_NUM_LTC_LTS_WAYS
Add gpu characteritics flag: NVGPU_L2_MAX_WAYS_EVICT_LAST_ENABLED to
allow userspace driver to determine if L2_MAX_WAYS_EVICT_LAST ioctl is
supported.
Bug 200605474
Change-Id: Id3180f891399f5e128500f3835d762aee59953e0
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2445884
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Nvgpu will move to new V2 device node hierarchy by default to be
consistent with MIG mode hierarchy. As part of this, expose V2 device
node hierarchy with this patch.
Both legacy and V2 hierarchies will co-exist for some duration until
V2 hierarchy is well tested out, and then legacy hierarchy will be
removed.
With V2 hierarchy, below is the directory structure for dev nodes :
igpu: /dev/nvgpu/igpu0/<dev_node>
dgpu: /dev/nvgpu/dgpu-0001\:01\:00.0/<dev_node>
Jira NVGPU-5648
Change-Id: I1c7a1c41e6d59fb248bc98a145c5ecebd06e8bad
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2443712
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WAR assume 1:1 IPA to PA mapping when hyp_read_ipa_pa_info fails for
the syncpt address which falls into syncpt shim aperture. API
nvgpu_mem_phys_sgl_ipa_to_pa() is taking care of IPA to PA mapping for
the syncpts which makes this WAR invalid.
Patch removes the WAR.
Bug 200673604
Change-Id: I966711e11c2ff1b5b5dd3f5e09674bea66c5d04b
Signed-off-by: prsethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2478068
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Add new MAPPING_MODIFY ioctl to the linux nvgpu driver.
This ioctl is used (for example) by the NvRmGpuMappingModify API to
change the kind of an existing mapping.
For compressed mappings the ioctl can be used to do the following:
* switch between two different compressed kinds
* switch between compressed and incompressed kinds
For incompressed mappings the ioctl can be used to do the following:
* switch between two different incompressed kinds
In order to properly update an existing mapping the nvgpu_mapped_buf
structure has been extended to cache the following state when the
mapping is first created:
* the compression tag offset (if applicable)
* the GMMU read/write flags
* the memory aperture
The unused ctag_lines field in the nvgpu_ctag_buffer_info structure
has been replaced with a new ctag_offset field.
Jira NVGPU-6374
Change-Id: I647ab9c2c272e3f9b52f1ccefc5e0de4577c14f1
Signed-off-by: scottl <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2468100
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Rename struct nvgpu_runlist_info to struct nvgpu_runlist; the
info is not necessary. struct nvgpu_runlist is soon to be a
first class object among the nvgpu object model.
Also rename the fields runlist_info and active_runlist_info to
simply runlists and active_runlists respectively. Again the info
text is just not necessary and somewhat misleading. These structs
_are_ the runlist representations in SW; they are not merely
informational.
Also add an rl_dbg() macro to print debug info specific to
runlist management and some debug prints specifying the runlist
topology for the running chip.
Change-Id: Id9fcbdd1a7227cb5f8c75cca4abbff94fe048e49
Signed-off-by: Alex Waterman <alexw@nvidia.com>
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The NEXT bit can remain set for the channel if timeslice expires before
scheduler clears it. Due to this nvgpu fails TSG unbind and in turn
nvrm_gpu fails channel close. In this case, checking the channel hw
state after some time can help see NEXT bit cleared by scheduler.
Reenable the tsg and return -EAGAIN to nvrm_gpu for it to retry again.
Bug 3144960
Change-Id: I35f417f02270e371a4e632986b73a00f8a4f921a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2468391
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For Linux v5.11, commit 6619ccf1bb1d ("dma-buf: Use struct dma_buf_map
in dma_buf_vmap() interfaces") changes to the dma_buf_vmap() and
dma_buf_vunmap() APIs to pass a new parameter of type
'struct dma_buf_map'. Update the NVGPU to support these updated APIs
for Linux v5.11+.
Finally, the legacy dma_buf_vmap() API returns NULL on error and not an
error code and so correct the test of the return value in the function
gk20a_cde_convert().
Bug 200687525
Change-Id: Ie20f101e965fa0f2c650d9b30ff4558ce1256c12
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2469555
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
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