Commit Graph

4 Commits

Author SHA1 Message Date
Amurthyreddy
710aab6ba4 gpu: nvgpu: MISRA 14.4 boolean fixes
MISRA rule 14.4 doesn't allow the usage of non-boolean variable as
boolean in the controlling expression of an if statement or an
iteration statement.

Fix violations where a non-boolean variable is used as a boolean in the
controlling expression of if and loop statements.

JIRA NVGPU-1022

Change-Id: I957f8ca1fa0eb00928c476960da1e6e420781c09
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1941002
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-11-07 10:35:13 -08:00
Srirangan Madhavan
ef5fdac7a6 gpu: nvgpu: Fix MISRA rule 15.6 violations
MISRA Rule-15.6 requires that all if-else blocks and loop blocks
be enclosed in braces, including single statement blocks. Fix errors
due to single statement if-else and loop blocks without braces
by introducing the braces.

JIRA NVGPU-775

Change-Id: Ib70621d39735abae3fd2eb7ccf77f36125e2d7b7
Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1928745
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-11-05 22:13:16 -08:00
Sagar Kamble
3030707936 gpu: nvgpu: init auto objects for MISRA 9.1
Address MISRA Rule 9.1 violation: The value of an object with automatic
storage duration shall not be read before it has been set.

JIRA NVGPU-881

Change-Id: I63fde303b0a3e05f16b9ce518684a37c774f0f43
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929824
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-10-23 15:44:50 -07:00
Mahantesh Kumbar
07cb84214b gpu: nvgpu: SEC2 IPC support
-Created sec2_ipc.c to support SEC2 IPC.
-Defined nvgpu_sec2_cmd_post() to send command
 to SEC2 RTOS from nvgpu along with dependent
 methods like seq acquire/release, validate &
 write cmd.
-Defined nvgpu_sec2_process_message() to
 process message from SEC2 RTOS & route
 to correct handler based on flag.
-Method sec2_process_init_msg() helps fetch
 parameters sent from SEC2 RTOS to setup
 queue, debug buffer as parameters.
-Created sec2 ops under gops to access
 sec2 engine specific HALs.
-Defined nvgpu_sec2_queue_init() init
 command & message for SEC2 RTOS using
 common falcon queue.
-Made Makefile changes to include sec2_ipc.c for build

JIRA NVGPUT-82

Change-Id: I6e4c2d6ec71aa61a543f34680d1412167c9a8cc6
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1828034
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-10-12 17:35:08 +05:30