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2 Commits

Author SHA1 Message Date
David Nieto
2029426446 gpu: nvgpu: gv1xx: resize patch buffer 
Follow the sizing consideration in bug 1753763 to support dynamic TPC modes
and subcontexts.

bug 200350539

Change-Id: Ibbdbf02f9c2ea3f082c1b2810ae7176b0775d461
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1584034
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2017-10-26 17:56:15 -07:00
David Nieto
ed8ac6e005 gpu: nvgpu: fix smid generation of perf tables 
SMID tables were generated according with the local tpc and the pagepool and cb
buffers from a different chip and did not take performance in consideration,
which made compute kernels hang with CTAs on the fly.

This change ensures we are using the right sizes and adds proper enumeration
of smids.

JIRA: NVGPUGV100-36
bug 2004378

Change-Id: Ic8f50c325d6d6720cca41d9740ae4f5f51e1100a
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1581664
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2017-10-20 11:55:43 -07:00