Prathap Kumar Valsan
321145b37e
gpu: nvgpu: Enable raw mode for compression
...
In raw addressing mode of CBC backing storage, comptaglines are not
required to be allocated or need to programmed in the ptes. Introduce a
flag to detect if the hardware supports raw mode and use that to skip
all the comptagline allocations and respective page table programming.
JIRA NVGPU-9717
Change-Id: I0a16881fc3e897c3c408b30d1835f30564649dad
Signed-off-by: Prathap Kumar Valsan <prathapk@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2908278
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2023-06-13 00:19:33 -07:00
Martin Radev
81d95456b9
gpu: nvgpu: Rename PLATFORM_ATOMIC to SYSTEM_COHERENT
...
To support current and future usecases, it would be
beneficial to select the SYSTEM_COHERENT aperture explicitly.
The benefits are:
- platform atomic code is cleaned-up.
- userspace can select the SYSTEM_COHERENT aperture for any
specific usecases.
Bug 3959027
Change-Id: I6489ebe87fa75cc760930277bad5e0cacca80eb6
Signed-off-by: Martin Radev <mradev@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2864177
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2023-04-21 11:31:53 -07:00
Vedashree Vidwans
2d24298af0
gpu: nvgpu: update nvgpu_pte_dbg_print function
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Currently, nvgpu_pte_dbg_print() overwrites ctag string "ctag=" and only
prints ctag number.
For example,
nvgpu_pte_dbg_print:104 [DBG] vm=3 PTE: i=0 size=8 |
GPU 0x1efc000000 phys 0x115a50000 pgsz: 4kb perm=RW kind=0x8 APT=SYSTEM C--V- 1
[0x08000010, 0x115a5007]
Update nvgpu_pte_dbg_print function to include ctag string.
nvgpu_pte_dbg_print:104 [DBG] vm=3 PTE: i=0 size=8 |
GPU 0x1efc000000 phys 0x115a50000 pgsz: 4kb perm=RW kind=0x8 APT=SYSTEM C--V- ctag=1
[0x08000010, 0x115a5007]
Jira NVGPU-5489
Change-Id: I2f84f89da685ad6a84534c0bb51e3ca1244b3497
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2354182
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2020-12-15 14:13:28 -06:00
Vedashree Vidwans
cd7194cbc0
gpu: nvgpu: modify gmmu page table entry functions
...
Move below chip agnostic gmmu pte functions to common/mm/gmmu/pte.c.
- gmmu_aperture_mask()
- pte_dbg_print()
Default big page size for all chips is 64K. So, move
gp10b_mm_get_default_big_page_size() to common file and rename as
nvgpu_gmmu_default_big_page_size().
Modify gv11b_gpu_phys_addr() to use get_iommu_bit() hal.
JIRA NVGPU-4666
Change-Id: I512c42723faf2d03e5b367879c9c385dcf52cdc2
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2329560
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2020-12-15 14:13:28 -06:00
