3 Commits

Author	SHA1	Message	Date
Sagar Kamble	5b55088970	gpu: nvgpu: skip subctx pdb init during as-channel bind ... While creating a new channel, ioctls are called in the below sequence: 1. GPU_IOCTL_OPEN_CHANNEL 2. AS_IOCTL_BIND_CHANNEL 3. TSG_IOCTL_BIND_CHANNEL_EX 4. CHANNEL_ALLOC_GPFIFO_EX 5. CHANNEL_ALLOC_OBJ_CTX. subctx pdbs and valid mask are programmed in the channel instance block in the channel ioctls AS_IOCTL_BIND_CHANNEL & CHANNEL_ALLOC_GPFIFO_EX. Programming them in the ioctl AS_IOCTL_BIND_CHANNEL is redundant. Remove related hal g->ops.mm.init_inst_block_for_subctxs. The hal init_inst_block will program context pdb and big page size. The hal init_inst_block_core will program context pdb, big page size and subctx 0 pdb. This is used by h/w units (fecs, pmu, hwpm, bar1, bar2, sec2, gsp, perfbuf etc.). For user channels, subctx pdbs are programmed as part of ramfc setup. Bug 3677982 Change-Id: I6656b002d513404c1fd7c3d349933e80cca7e604 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2680907 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>	2022-06-28 23:33:31 -07:00
Lakshmanan M	c0e2dc5b74	gpu: nvgpu: Add subctx programming for MIG ... This CL covers the following code changes, 1) Added api to init inst_block for more than one subctxs. 2) Added logic to limit the subctx bind based on max. VEID count allocated to a gr instance. 3) Renamed nvgpu_grmgr_get_gr_runlist_id. JIRA NVGPU-5647 Change-Id: Ifec8164a9e5f46fbd0538c3dd50e19ee63667a54 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2418463 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com> Reviewed-by: Dinesh T <dt@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit	2020-12-15 14:13:28 -06:00
Alex Waterman	6c2c4181ae	gpu: nvgpu: Create hal.mm.mm for misc MM HALs ... There are many miscellaneous HALs for various MM related functionality. This patch aims to migrate all the remaining MM code from the <chip>/ mm_<chip>.[ch] files in HAL files under hal/. Much of this is fairly straightforward copy/paste and updates to the HAL init files. The exception to that is the move of the left over gv11b MMU fault handling code in mm_gv11b.c. Having both a hal/mm/mm/mm_gv11b.c and a gv11b/mm_gv11b.c file causes tmake to choke so the gv11b/mm_gv11b.c file was moved to gv11b/mmu_fault_gv11b.c. This will be cleaned up in a subsequent patch. JIRA NVGPU-2042 Change-Id: I12896de865d890a61afbcb71159cff486119ffb8 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2109050 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-05-01 15:06:57 -07:00